[We-P] Poster Presentation

[We-P-11] Influence of Shallow Pits and Device Design of 4H-SiC VDMOS Transistors on In-line Defect Analysis by using PL Scanning

*Matthias Kocher¹, Holger Schlichting¹, Birgit Kallinger¹, Mathias Rommel¹, Anton J. Bauer¹, Tobias Erlbacher^1,2 (1. Fraunhofer Institute for Integrated Systems and Device Technology(Germany), 2. Friedrich-Alexander-Univ. Erlangen-Nuernberg(Germany))