The 61st JSAP Spring Meeting, 2014

Presentation information

Oral presentation

13. Semiconductors A (Silicon) » 13.3 Si Process・Interconnect・MEMS・Integration

[18p-E14-1~21] 13.3 Si Process・Interconnect・MEMS・Integration

Tue. Mar 18, 2014 1:15 PM - 6:45 PM E14 (E302)

2:15 PM - 2:30 PM

[18p-E14-5] Fabrication of Three-Dimensional Integrated Circuits by using Au/SiO2 Hybrid Bonding

Masahide Goto1, Kei Hagiwara1, Yoshinori Iguchi1, Hiroshi Ohtake1, Takuya Saraya2, Eiji Higurashi2, Hiroshi Toshiyoshi2, Toshiro Hiramoto2 (NHK STRL1, Univ. of Tokyo2)

Keywords:3次元集積回路,接合,撮像デバイス