[11a-N205-1~11] CS.9 6.1 強誘電体薄膜、13.3 絶縁膜技術、13.5 デバイス／配線／集積化技術のコードシェアセッション

▼ [11a-N205-9] Simulation Study on the Role of GIDL Current for Erase Operation in FeFETs

〇(M2)Xiaoran Mei¹、Fei Mo¹、Toshiro Hiramoto¹、Masaharu Kobayashi¹ (1.IIS, Univ. of Tokyo)

キーワード：FeFET, GIDL

FeFET memory, as a kind of state-of-the-art non-volatile memory, has been in the limelight for its small cell size, low-power and high-speed operation since CMOS compatible ferroelectric (FE)-HfO2 was discovered. Previously, 3D vertical structure has become the mainstream in NAND flash memory, with its characteristics of 1. N-type junctionless transistor and floating-body as 1T memory , which accelerates the generation of majority carrier(electron) and 2. GIDL (Gate Induced Drain Leakage) current for fast generation & supply of minority carriers(hole) , which means efficient erase operation. Therefore, it is natural to consider the same structure and utilize GIDL current for higher performance in FeFET memory. In this work, we investigate the role of GIDL current for erase operation toward 3D vertical FeFET by TCAD simulation, in terms of gate/drain overlap and underlap cases, low/high sweep speed of gate voltage and drain voltage dependence.