[Session 1] Thermal/Mechanical Simulations

[Session_1-05] Full Chip Stress Model for Flash BEOL Crack Failure Risk Analysis

*Kyungmi Yeom¹, Geunsang Yoo¹, Anthony Payet², Alexander Schmidt¹, Hyoshin Ahn¹, Inkook Jang¹, Yutaka Nishizawa², Masaru Uchiyama², Yasuyuki Kayama², Satoru Yamada², Dae Sin Kim¹ (1. CSE Team, Innovation Center, Samsung Electronics, 2. DSRJ)