[AMD1-3] Device Model of Positive Bias Temperature Stress Instability for Oxide Semiconductor TFTs
AMD Workshop
Positive bias temperature stress instability, Oxide semiconductor TFT, Device simulation
We propose a device model for oxide semiconductor thin-film transistors (OS TFTs) under positive bias temperature stress (PBTS). This model is a function of the channel interface electric field, and device simulations using this model reproduce measured PBTS degradation. The model is suitable for PBTS instability evaluation of OS TFTs.