[F-1-6] A Physical Model for Hole Direct Tunneling Currents Through Ultrathin Gate Dielectrics in Advanced CMOS Devices

Y. T. Hou, M. F. Li, W. H. Lai, Y. Jin (1.Silicon Nano Device Lab, Department of Electrical & Computer Engineering National University of Singapore, 2.Chartered Semiconductor Manufacturing Ltd)

https://doi.org/10.7567/SSDM.2001.F-1-6