[C-7-1] Experimental Study of PVD-TiN Gate with Poly-Si Capping and Its Application to 20 nm FinFET Fabrication

T. Kamei¹、Y. X. Liu²、K. Endo²、S. O'uchi²、J. Tsukada²、H. Yamauchi²、Y. Ishikawa²、T. Hayashida¹、T. Matsukawa²、K. Sakamoto²、A. Ogura¹、M. Masahara² (1.Meiji Univ.、2.AIST , Japan)

https://doi.org/10.7567/SSDM.2010.C-7-1