[TuePM1A] (Regular Session) Signal and Power Integrity (1)

[TuePM1A.6] ^★Closed-Loop Structure for Mitigating Jitter-Induced Noise of Clock Source in High-Bandwidth Signal Sampling

^○Haojie Wu(Zhejiang University), Xiangyu Meng(Zhejiang University), Qidong Bao(Zhejiang University), Wenrui Wang(Zhejiang University), Yin Sun(Missouri University of Science and Technology), Xinglin Sun(Zhejiang University)