8:45 AM - 9:00 AM
*Takuma Kobayashi1, Yu-ichiro Matsushita1 (1. Tokyo Inst. of Tech.(Japan))
Oral Presentation
MOS Gate Stacks and Device Processing
Wed. Oct 2, 2019 8:45 AM - 10:15 AM Room A (Kyoto International Conference Center)
8:45 AM - 9:00 AM
*Takuma Kobayashi1, Yu-ichiro Matsushita1 (1. Tokyo Inst. of Tech.(Japan))
9:00 AM - 9:15 AM
*Takahide Umeda1, Takuma Kobayashi2, Yu-ichro Matsushita2, Eito Higa1, Hiroshi Yano1, Mitsuru Sometani3, Shinsuke Harada3 (1. Univ. of Tsukuba(Japan), 2. Tokyo Inst. of Tech.(Japan), 3. AIST(Japan))
9:15 AM - 9:30 AM
*Mark Anders1, Patrick M Lenahan2, Arthur H Edwards3, Peter A Schultz4, Renee M Van Ginhoven3 (1. National Institute of Standards and Technology(United States of America), 2. Pennsylvania State University(United States of America), 3. Air Force Research Laboratory(United States of America), 4. Sandia National Laboratories(United States of America))
9:30 AM - 9:45 AM
*James P. Ashton1, Patrick M. Lenahan1, Daniel J. Lichtenwalner2, Mark A. Anders3, Aivars J. Lelis4 (1. Penn State Univ.(United States of America), 2. Wolfspeed, a Cree Company(United States of America), 3. National Inst. of Standards and Tech.(United States of America), 4. United States Army Res. Labs.(United States of America))
9:45 AM - 10:00 AM
*Yu-ichiro Matsushita1, Tetsuo Hatakeyama2 (1. Tokyo Inst. of Tech.(Japan), 2. Toyama Prefectural Univ.(Japan))
10:00 AM - 10:15 AM
*Eito Higa1, Mitsuru Sometani2, Shinsuke Harada2, Hiroshi Yano1, Takahide Umeda1 (1. Univ. of Tsukuba.(Japan), 2. National Inst. of Advanced Indus. Sci. and Tech.(Japan))
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