Oral Presentation
MOS Gate Stacks and Device Processing
Wed. Oct 2, 2019 10:45 AM - 12:15 PM Room A (Kyoto International Conference Center)
10:45 AM - 11:15 AM
*Munetaka Noguchi1, Toshiaki Iwamatsu1, Hiroyuki Amishiro1, Hiroshi Watanabe1, Koji Kita2, Naruhisa Miura1 (1. Advanced Technology R & D Center, Mitsubishi Electric Corporation(Japan), 2. Department of Materials Engineering, The University of Tokyo(Japan))
Schedule
11:15 AM - 11:30 AM
*Tetsuo Hatakeyama1,2, Minoru Sometani2, Hirohisa Hirai2, Shinsuke Harada2 (1. Toyama Pref. Univ.(Japan), 2. AIST(Japan))
Schedule
11:30 AM - 11:45 AM
*Hajime Tanaka1,2, Nobuya Mori1 (1. Osaka Univ.(Japan), 2. Kyoto Univ.(Japan))
Schedule
11:45 AM - 12:00 PM
*Hirohisa Hirai1, Tetsuo Hatakeyama1, Mitsuru Sometani1, Mitsuo Okamoto1, Shinsuke Harada1, Hajime Okumura1 (1. AIST(Japan))
Schedule
12:00 PM - 12:15 PM
*Judith Woerle1,2, Brett Johnson3, Corrado Bongiorno4, Kohei Yamasue5, Gabriel Ferro6, Dipanwita Dutta2, Yasuo Cho5, Ulrike Grossner1, Massimo Camarda2,1 (1. ETH Zurich(Switzerland), 2. Paul Scherrer Institute(Switzerland), 3. University of Melbourne(Australia), 4. IMM-CNR Catania (Italy), 5. Tohoku University(Japan), 6. Université de Lyon(France))
Schedule
Abstract password authentication.
Password is required to view the abstract. Please enter a password to authenticate.
Please log in with your participant account.
» Participant Log In