[G] Packaging

[259] Delamination Analysis of Stacked Via in High-Density-Multilayer Printed Wiring Boards by FEA

*Moe NOZAKI¹, Yoshiharu KARIYA², Yoshiyuki HIROSHIMA³, Nobuo TAKETOMI³, Kenichi OHASHI⁴, Kenichi TOMIOKA⁴, Shunichi KIKUCHI⁵, Jack TAN⁵ (1. Graduate school of Shibaura Institute of Technology, 2. Department of Material Science and Engineering, Shibaura Institute of Technology, 3. NTT Electronics Cross Technology Corp., 4. Showa Denko Materials Co., Ltd, 5. HDP User Group, Inc)

Keywords:Stacked Via、Finite Element Analysis、Printed Wiring Boards、Delamination analysis

有限要素法解析によりスタックビア界面の破壊駆動力を破壊力学的に評価し，ビア界面破壊におよぼす影響因子を調査し，破壊の防止のための設計指針を得た．