[SS-03] Design of an LUT-Shift Function for Nonvolatile FPGA-Based Biniarized-Convolutional Neural Network Accelerator
Keywords:BCNN, FPGA, LUT, Nonvolatile logic, Power gating
Special Session
JNNS2020 » Special Session
Fri. Dec 4, 2020 10:00 AM - 12:00 PM Oral Session (Zoom)
Chair:Takahiro Hanyu(RIEC, Tohoku University)
Keywords:BCNN, FPGA, LUT, Nonvolatile logic, Power gating