Japan Geoscience Union Meeting 2014

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Oral

Symbol S (Solid Earth Sciences) » S-TT Technology & Techniques

[S-TT60_30PM1] Creating future of solid Earth science with high performance computing (HPC)

Wed. Apr 30, 2014 2:15 PM - 4:00 PM 211 (2F)

Convener:*Ryota Hino(International Research Institute of Disaster Science, Tohoku University), Yoshimori Honkura(Volcanic Fluid Research Center, Tokyo Institute of Technology), Yoshiyuki Kaneda(Japan Agency for Marine-Earth Science and Technology), Taro Arikawa(Port and Airport Research Institute), Tsuyoshi Ichimura(Earthquake Research Institute,The University of Tokyo), Masaru Todoriki(Center for Integrated Disaster Information Research / Earthquake Research Institute, The University of Tokyo), Takane Hori(Earthquake and Tsunami Research Project for Disaster Prevention, Japan Agency for Marine-Earth Science and Technology), Chair:Takane Hori(Earthquake and Tsunami Research Project for Disaster Prevention, Japan Agency for Marine-Earth Science and Technology), tsuyoshi ichimura(Earthquake Research Institute,The University of Tokyo)

3:54 PM - 4:00 PM

[STT60-P01_PG] Parallel Performance of Particle Method in Many-Core System

3-min talk in an oral session

*Mikito FURUICHI1, Daisuke NISHIURA1 (1.Japan Agency for Marine-Earth Science and Technology)

Keywords:high-performance computing, many core, SPH, Parallel Computing, Performance analysis, Shared memory

We present a computational performance of the smoothed particle hydrodynamics (SPH) simulation on three types of current shared-memory parallel computer devices: many integrated core (MIC: Intel Xeon Phi) processor, graphics processing units (GPU: Nvidia Geforce GTX Titan), and multi-core Central Processing Unit (CPU: Intel Xeon E5-2680 and Fujitsu SPARC64 processors). We are especially interested in the efficient shared-memory allocation methods with proper data access patterns on each chipset. We first introduce several parallel implementation techniques of SPH code for shared-memory system. Then they are examined on our target architectures to find the best algorithms for each processor unit. In addition, the computing and the power efficiency, which are increasingly important to compare multi device computer systems, are also examined for SPH calculation. In our bench mark test, GPU is found to mark the best arithmetic performance as the standalone device and the most efficient power consumption. The multi-core CPU shows the best computing efficiency. On the other hand, the computational speed by the MIC on Xeon Phi approached to that by two Xeon CPUs. This indicates that using MIC is attractive choice for the existing SPH codes parallelized by OpenMP to gain the computational acceleration by the many many-core processors.