Japan Geoscience Union Meeting 2016

Presentation information


Symbol P (Space and Planetary Sciences) » P-CG Complex & General

[P-CG20] Status and perspective of future missions and their instruments and technologies for space sciences

Tue. May 24, 2016 9:00 AM - 10:30 AM 203 (2F)

Convener:*Ichiro Yoshikawa(The University of Tokyo), Yoshiya Kasahara(Information Media Center, Kanazawa University), Chair:Keigo Ishisaka(Toyama Prefectural University), Yoshiya Kasahara(Information Media Center, Kanazawa University)

9:15 AM - 9:30 AM

[PCG20-02] Digital Data Processing Module in the Low Frequency Analyzer System (LFAS) for the SS520-3 Rocket Experiment

*Yoshiya Kasahara1, Tsubasa Takahashi1, Mamoru Ota1, Hirotsugu Kojima2, Mitsunori Ozaki1, Satoshi Yagitani1, Keigo Ishisaka3 (1.Information Media Center, Kanazawa University, 2.Kyoto University, 3.Toyama Prefectural University)

Keywords: Plasma Wave Receiver, SS520-3 rocket, Digital signal processing

We introduce a digital data processing module for low frequency analyzer system (LFAS) on the “SS-520-3” rocket. The main objective of the SS520-3 rocket experiment is to identify ion acceleration and heating mechanism in the polar cusp region. The LFAS is equipped with two type of receivers; EFD (electric field) and WFC (waveform capture). The EFD measures electric wave field in the frequency range from DC to 400 Hz and the data will be sent by analogue telemetry, while WFC covers electric field measurements in the VLF range below 10 kHz and generate digital data which consist of one channel of spectrum and two channels of waveform. In order to achieve real-time data processing of the WFC receiver on the rocket, we plan to develop digital data processing modules on FPGA. The digital modules consist of three FFT modules with cascaded decimation filters for spectrum analyzers and a lossy data compression module for waveform data for the purpose of data reduction. We have already developed a general-purpose FPGA board for evaluation of various kinds of signal processing [1]. We can integrate our own signal processing module on it without any complicated wiring work for the peripheral circuits and evaluate the performance of our proposed module. In the presentation, we report the current design of these data processing modules.
[1] Y. Kasahara, H. Matsui, and Y. Goto, Abstract of JPGU Meeting 2015, PCG31-19.