Poster presentation

14. Semiconductors B (Exploratory Materials, Physical Properties, Devices) » 14.3 Electron devices and Process technology

[19p-PB2-1~19] 14.3 Electron devices and Process technology

Fri. Sep 19, 2014 1:30 PM - 3:30 PM PB2 (Gymnasium2)

ポスター掲示時間13:30～15:30(PB2会場)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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1:30 PM - 3:30 PM

[19p-PB2-1] Surface defects of low-Mg-doped p-AlGaN and p-InGaN Schottky contacts

^○Toshichika Aoki¹, Kenji Shiojima¹ (University of Fukui¹)

1:30 PM - 3:30 PM

[19p-PB2-2] Influence of Surface Treatments on Ni/AlGaN/GaN Schottky Characteristics (2)

^○(M2)ariabasu arusaruman¹, takayuki sawada¹, kazuhiko suzuki¹, takahiru masuda¹ (hokkaido University of Science¹)

1:30 PM - 3:30 PM

[19p-PB2-3] Application of Al₂O₃/InAlN interface formed by 2-step ALD to MOSHEMT

^○Yoichiro Odanagi¹, Masamichi Akazawa¹, Asubar Joel¹, Zenji Yatabe¹, Tamotsu Hashizume¹ (Hokkaido Univ.¹)

1:30 PM - 3:30 PM

[19p-PB2-4] Characterization of traps in AlGaN/GaN HEMTs on Si by drain conductance DLTS

^○Kazuki Miyamoto¹, Yutaka Tokuda¹, Hiroyuki Ueda², Takashi Katuno², Toru Kachi² (Aichi Inst. of Technol.¹, Toyota Central R&D Lab.,Inc.²)

1:30 PM - 3:30 PM

[19p-PB2-5] C-t Evaluation of Turn-On Recovery Characteristics in AlGaN/GaN Hetero-Structures

^○Yoshitaka Nakano¹, Yoshihiro Irokawa², Masatomo Sumiya², Shuichi Yagi³, Hiroji Kawai³ (Chubu Univ.¹, NIMS², POWDEC³)

1:30 PM - 3:30 PM

[19p-PB2-6] Electrical Characterization of HVPE-GaN films with Ar⁺ Ion Bombardment

^○Yoshitaka Nakano¹, Keiji Nakamura¹, Masahito Niibe², Retsuo Kawakami³ (Chubu Univ.¹, Univ. Hyogo², Univ. Tokushima³)

1:30 PM - 3:30 PM

[19p-PB2-7] RF Characteristics of AlGaN/GaN HEMTs with Slant Field Plates

^○Shinya Hatakeyama¹, Kengo Kobayashi¹, Tomohiro Yoshida¹, Taiichi Otsuji¹, Tetsuya Suemitsu¹ (RIEC, Tohoku Univ.¹)

1:30 PM - 3:30 PM

[19p-PB2-8] Chemical Vapor Deposition of Silicon-based Insulator Films Enhanced by Surface-Wave Plasma and Application to Nitride Devices

^○Hiroshi Okada^1,2, Kyohei Kawakami², Takahiro Ishimaru², Masatoshi Shinohara², Masakazu Furukawa³, Akihiro Wakahara^2,1, Hiroto Sekiguchi² (EIIRIS¹, Toyohashi Tech², Aries Research Group³)

1:30 PM - 3:30 PM

[19p-PB2-9] Formation of p-n Junction by Mg Ion Implantation to n--GaN Epitaxial Layers on Free-Standing GaN Substrates

^○(M1)Yusuke Saijo¹, Takuya Oikawa¹, Shigeki Kato¹, Tomoyosi Mishima¹, Tohru Nakamura¹ (Hosei Univ.¹)

1:30 PM - 3:30 PM

[19p-PB2-10] Normally-off GaN MISFETs Using Ion Implantation of Magnesium

^○Hayao Kasai¹, Takuya Oikawa¹, Jun Kimura¹, Tomoyoshi Mishima¹, Tohru Nakamura¹ (Hosei univ.¹)

1:30 PM - 3:30 PM

[19p-PB2-11] High Power Operation of Self-aligned Ion-implanted MISFETs on p-GaN Substrates

^○(M1)Jun Kimura¹, Hayao Kasai¹, Tohru Nakamura¹, Tomoyosi Misima¹ (Hosei¹)

1:30 PM - 3:30 PM

[19p-PB2-12] Ion-implanted Vertical Bipolar Transistor on Free-Standing GaN Substrates

^○(M2)Kengo Takahashi¹, Kazuki Nomoto², Tomoyoshi Mishima¹, Tohru Nakamura¹ (Hosei Univ.¹, University of Notre Dame.²)

1:30 PM - 3:30 PM

[19p-PB2-13] Effects of SiO₂ deposition process on formation of contacts to 2D hole gas layers

^○Shunsuke Kubota¹, Rei Kayanuma¹, Akira Nakajima³, Shin-ichi Nishizawa³, Hiromichi Ohashi^2,3, Kazuo Tsutsui¹, Kuniyuki Kakushima¹, Hitoshi Wakabayashi¹, Hiroshi Iwai² (Tokyo Tech. IGSSE¹, Tokyo Tech. FRC², AIST³)

1:30 PM - 3:30 PM

[19p-PB2-14] 600 V Switching Characteristics of GaN Polarization Super Junction (PSJ) Transistor on Sapphire

^○Shuichi Yagi¹, Shoko Hirata¹, Fumihiko Nakamura¹, Sota Matsumoto¹, Hironori Nakamura¹, Hiroji Kawai¹ (POWDEC K.K.¹)

1:30 PM - 3:30 PM

[19p-PB2-15] NOx gas sensing properties for Pd/ZnO/GaN heterojunction Diodes

^○Shu Fujita¹, Makoto Miyoshi¹, Takashi Egawa¹ (Nagoya Inst. of Tech.¹)

1:30 PM - 3:30 PM

[19p-PB2-16] Physical mechanism for optical gain in InGaAs-MSM-PDs

^○Shunsuke Sugiyama¹, Yui Nishio¹, Marie Sato¹, Shusaku Hirata¹, Takato Sato¹, Naomi Hirayama¹, Tsutomu Iida¹, Yoshifumi Takanashi¹ (TUS¹)

1:30 PM - 3:30 PM

[19p-PB2-17] Gate voltage shift caused by accumulated holes in InAs PHEMTs

^○Yui Nishio¹, Shunsuke Sugiyama¹, Marie Sato¹, Shusaku Hirata¹, Takato Sato¹, Naomi Hirayama¹, Tsutomu Iida¹, Yoshifumi Takanashi¹ (TUS¹)

1:30 PM - 3:30 PM

[19p-PB2-18] Output power characteristics of InGaAs/InAlAs HEMT at 90-GHz frequency band

^○Issei Watanabe¹, Akira Endoh^1,2, Akifumi Kasamatsu¹, Takashi Mimura^1,2 (NICT¹, Fujitsu Lab. Ltd.²)

1:30 PM - 3:30 PM

[19p-PB2-19] Monte Carlo Simulation of InAlAs/InGaAs HEMTs with Various Shape of Buried Gate

^○Akira Endoh^1,2, Issei Watanabe¹, Akifumi Kasamatsu¹, Takashi Mimura^1,2 (Nat. Inst. of Info. & Com. Tech.¹, Fujitsu Labs. Ltd.²)

Session information

[19p-PB2-1~19] 14.3 Electron devices and Process technology