Electrical control of potential barrier with Si-SET attached multiple gate electrodes

Presentation information

Poster presentation

13. Semiconductors A (Silicon) » 13.4 Devices/Integration Technologies

Wed. Sep 17, 2014 9:30 AM - 11:30 AM PA3 (Gymnasium1)

ポスター掲示時間9:30～11:30(PA3会場)

9:30 AM - 11:30 AM

^○Takafumi Uchida¹, Isamu Yoshioka¹, Hikaru Sato¹, Masashi Arita¹, Akira Fujiwara², Yasuo Takahashi¹ (IST.Hokkaido Univ.¹, NTT Basic Research Labs.²)

Keywords:量子ドット,単電子