[19p-A19-1~15] 13.3 Si Process・Interconnect・MEMS・Integration

[19p-A19-13] Evaluation of Plasma-Damage Effects on Transistor Performance in Via-last Backside-via Process for 3D IC

^○Yohei Sugawara¹, hideto Hashiguchi¹, seiya Tanikawa¹, hisashi Kino², Takahumi Fukushima³, Kang-Wook Lee³, Mitumasa Koyanagi³, Tetsu Tanaka^1,2 (Tohoku Univ.¹, Tohoku Univ.², Tohoku Univ.³)

Keywords:半導体,三次元集積回路,TSV