[13p-PA5-1~4] 13.3 Insulator technology

[13p-PA5-4] Development of Deposition Technology of Gate SiO₂ Layer for GaN Power Transistors

〇Takuya Maekawa¹, Shota Takagi¹, Tetsuji Arai¹, Keisuke Arimoto¹, Junji Yamanaka¹, Kiyokazu Nakagawa¹, Toshiyuki Takamatsu², Katsunori Ueno³ (1.Yamanashi Univ., 2.SST, 3.Fujidenki)

Keywords:GaN Power Transistors,Gate SiO2 Layer