2015年 第76回応用物理学会秋季学術講演会

講演情報

一般セッション(口頭講演)

13 半導体 » 13.4 Siプロセス・配線・MEMS・集積化技術

[14p-1C-1~16] 13.4 Siプロセス・配線・MEMS・集積化技術

2015年9月14日(月) 13:15 〜 17:30 1C (135)

座長:中村 友二(富士通研),筑根 敦弘(大陽日酸)

14:30 〜 14:45

[14p-1C-6] Characteristic study of PVD-Co(W) single barrier/liner for highly reliable ULSI Cu interconnects

〇(DC)金 泰雄1、Momose Takeshi1、Takaaki Tsunoda2、Moriwaki Takayuki2、Nakagawa Takashi2、Shimogaki Yukihiro1 (1.The Univ. of Tokyo、2.CANON ANELVA CORPORATION)

キーワード:PVD-Co(W)、barrier layer、liner layer

In semiconductor device, Cu interconnect is buried in low-dielectric-constant (low-k) materials with interlayers [1]. These are double layers of TaN and Ta, serving as barrier against Cu diffusion and liner, rspectively [2]. With continued downscaling of the device dimensions [3], these layers cause some critical reliability issues such as electromigration (EM) failure, short-circuit failure, and resistive-capacitive (RC) signal delay. Introduction of new materials is beneficial to EM failure and short-circuit failure. However, it cannot relieve RC delay. Meanwhile, single barrier/liner has potential to solve all three issues because transition from double layer to single layer can decrease RC delay as well.
In this context, we previously demonstrated the high performances of ALD-Co(W) superior to PVD-Ta/TaN [5]. More recently, we reported that PVD-Co(W) exhibited these three performances superior to both PVD-Ta/TaN and ALD-Co(W) [4]. However, in the evaluation of diffusion barrier property of PVD-Co(W), we found that we underestimated the barrier property. In this research, we evaluated the barrier property correlctly by employing new measurement method using XPS, that is called back-side measurement.