The 76th JSAP Autumn Meeting, 2015

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13 Semiconductors » 13.5 Semiconductor devices and related technologies

[15p-1C-1~18] 13.5 Semiconductor devices and related technologies

Tue. Sep 15, 2015 1:15 PM - 6:00 PM 1C (135)

座長:齋藤 真澄(東芝),入沢 寿史(産総研)

5:00 PM - 5:15 PM

[15p-1C-15] Effect of temperature and gate bias tuning on phase transition of 1T-TaS2

〇Shigehisa Shibayama1,2, Nan Fang1, Takeaki Yajima1, Tomonori Nishimura1, Kousuke Nagashio1, Akira Toriumi1 (1.The Univ. of Tokyo, 2.JSPS research fellow)

Keywords:1T-TaS2,mono layer,Gate bias