[12a-D5-1~8] 15.5 Group IV crystals and alloys

Thu. Mar 12, 2015 10:00 AM - 12:00 PM D5 (16-205)

△：Young Scientist Oral Presentation Award Applied
▲：English Presentation
▼：Both Award Applied and English Presentation

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10:00 AM - 10:15 AM

[12a-D5-1] Formation of Ge thin films on Si(100) by using thermal annealing for sub-monolayer carbon on amorphous Ge

〇takuma aoyama¹, yuhki itoh², shinji hatakeyama², tomoyuki kawashima^1,², katsuyoshi washio^1,² (1.Tohoku Univ., 2.Grad.Schl.of Eng.,Tohoku Univ)

10:15 AM - 10:30 AM

△ [12a-D5-2] Formation of Ge films in sub-monolayer carbon/Ge/Si(100) structure under the influence of growth temperature

〇(M2)Yuki Ito¹, Shinji Hatakeyama¹, Tomoyuki Kawashima¹, Katsuyoshi Washio¹ (1.Tohoku Univ.)

10:30 AM - 10:45 AM

[12a-D5-3] Effect of Si-C reaction temperature on Ge dots using sub-monolayer carbon on Si(100)

〇Yuhki Satoh¹, Yuhki Itoh¹, Tomoyuki Kawashima¹, Katsuyoshi Washio¹ (1.Tohoku Univ.)

10:45 AM - 11:00 AM

[12a-D5-4] Fabrication of compressively strained Si/relaxed Si_1-xC_x heterostructures utilizing Ar ion implantation technique

〇You Arisawa¹, Hoshi Yusuke¹, Fujiwara Kousuke², Yamanaka Junji², Arimoto keisuke², Nakagawa Kiyokazu², Sawano Kentarou³, Usami Noritaka¹ (1.Nagoya Univ., 2.Univ. of Yamanashi, 3.Tokyo City Univ.)

11:00 AM - 11:15 AM

△ [12a-D5-5] Suppression effect of the segregation on delta-doped P in n-Ge by the insertion of Si layer

〇Michihiro Yamada¹, Kentarou Sawano², Masashi Uematsu¹, Kohei Itoh¹ (1.Keio Univ., 2.Tokyyo City Univ.)

11:15 AM - 11:30 AM

[12a-D5-6] Flattening of two-step-growth Ge thin film on Si(100) by using MBE

〇Ryo Hayase¹, Yuhki Itoh¹, Tomoyuki Kawashima¹, Katsuyoshi Washio¹ (1.Tohoku Univ.)

11:30 AM - 11:45 AM

[12a-D5-7] Properties of Single Crystal Ge Layers Fabricated by Two-Step Epitaxial Growth

〇Katsuya Oda¹, Tadashi Okumura¹, Jun-ichi Kasai¹, Tatemi Ido¹ (1.Hitachi Central Research Lab.)

11:45 AM - 12:00 PM

[12a-D5-8] Improvements of electrical properties of wafer-bonded GeOI substrates with ultrathin Al₂O₃/SiO₂BOX layers by post-annealing

〇Keisuke Yoshida¹, Yoshiaki Nakamura¹, Shotaro Takeuchi¹, Yoshihiko Moriyama^1,², Tsutomu Tezuka², Akira Sakai¹ (1.Osaka Univ., 2.GNC-AIST)

Session information

[12a-D5-1~8] 15.5 Group IV crystals and alloys

[12a-D5-1] Formation of Ge thin films on Si(100) by using thermal annealing for sub-monolayer carbon on amorphous Ge

△ [12a-D5-2] Formation of Ge films in sub-monolayer carbon/Ge/Si(100) structure under the influence of growth temperature

[12a-D5-3] Effect of Si-C reaction temperature on Ge dots using sub-monolayer carbon on Si(100)

[12a-D5-4] Fabrication of compressively strained Si/relaxed Si_1-xC_x heterostructures utilizing Ar ion implantation technique

△ [12a-D5-5] Suppression effect of the segregation on delta-doped P in n-Ge by the insertion of Si layer

[12a-D5-6] Flattening of two-step-growth Ge thin film on Si(100) by using MBE

[12a-D5-7] Properties of Single Crystal Ge Layers Fabricated by Two-Step Epitaxial Growth

[12a-D5-8] Improvements of electrical properties of wafer-bonded GeOI substrates with ultrathin Al₂O₃/SiO₂BOX layers by post-annealing

Authentication

Session information

[12a-D5-1~8] 15.5 Group IV crystals and alloys

[12a-D5-1] Formation of Ge thin films on Si(100) by using thermal annealing for sub-monolayer carbon on amorphous Ge

△ [12a-D5-2] Formation of Ge films in sub-monolayer carbon/Ge/Si(100) structure under the influence of growth temperature

[12a-D5-3] Effect of Si-C reaction temperature on Ge dots using sub-monolayer carbon on Si(100)

[12a-D5-4] Fabrication of compressively strained Si/relaxed Si1-xCx heterostructures utilizing Ar ion implantation technique

△ [12a-D5-5] Suppression effect of the segregation on delta-doped P in n-Ge by the insertion of Si layer

[12a-D5-6] Flattening of two-step-growth Ge thin film on Si(100) by using MBE

[12a-D5-7] Properties of Single Crystal Ge Layers Fabricated by Two-Step Epitaxial Growth

[12a-D5-8] Improvements of electrical properties of wafer-bonded GeOI substrates with ultrathin Al2O3/SiO2 BOX layers by post-annealing

Authentication

[12a-D5-4] Fabrication of compressively strained Si/relaxed Si_1-xC_x heterostructures utilizing Ar ion implantation technique

[12a-D5-8] Improvements of electrical properties of wafer-bonded GeOI substrates with ultrathin Al₂O₃/SiO₂BOX layers by post-annealing