The 63rd JSAP Spring Meeting, 2016

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[20p-S422-1~18] 13.5 Semiconductor devices and related technologies

Sun. Mar 20, 2016 1:45 PM - 6:30 PM S422 (S4)

Keiji Ikeda(TOSHIBA), Jiro Ida(Kanazawa Inst. of Tech.)

4:00 PM - 4:15 PM

[20p-S422-10] Contribution to Off-Current of Source-Drain Direct Tunneling in Short-Channel TFET

Wenbo Lin1, Shinjiro Iwata1, Koichi Fukuda1,2, Yasuyuki Miyamoto1 (1.Tokyo Tech., 2.AIST.)

Keywords:Tunnel FET

Source-drain direct tunneling is problem in tunnel FET under short gate length for reduction of dynamic power. To estimate component of direct tuneling, numerical simulation of type-II heterojunction tunnel FET is carried out. Component of source-drain direct tunneling is dominant when the gate length is 10nm and ambipolar components is suppressed by reduction of drain carrier concentraion. Thus, direct tunneling may become a bottleneck in the short channel tunnel FET.