[5a-C17-1~10] 13.8 化合物及びパワー電子デバイス・プロセス技術

▲ [5a-C17-6] Planar Vertical Ga₂O₃ MOSFETs with a Current Aperture

〇ManHoi Wong¹、Ken Goto^2,3、Akito Kuramata²、Shigenobu Yamakoshi²、Hisashi Murakami³、Yoshinao Kumagai³、Masataka Higashiwaki¹ (1.NICT、2.Tamura Corp.、3.Tokyo Univ. Agricul. Technol.)

キーワード：Ga2O3, vertical MOSFET, ion implantation

Vertical power transistors are preferred over their lateral counterparts since chip area utilization is more efficient and device operation is insensitive to surface effects. This paper presents the first demonstration of a vertical Ga₂O₃ metal-oxide-semiconductor field-effect transistor, wherein the source was electrically isolated from the drain by a current blocking layer (CBL) except at an aperture opening through which drain current was conducted. Similar to Si and SiC technologies, this planar structure was fabricated with no regrowth steps. Successful transistor action was realized by gating a channel above the CBL.