2:00 PM - 2:15 PM
▲ [19p-234B-4] Improvement of SiGe MOS Interfaces Properties by TiN/Y2O3 Gate Stacks
Keywords:SiGe, high-k materials, interface trap density
A SiGe MOSFET is a promising solution to realize high performance LSIs under the traditional scaling by the Moore's law. Strained SiGe grown on Si has larger hole mobility and smaller hole effective mass than Si. Here, the formation of the superior high-k/SiGe MOS interfaces is important for realizing high-performance CMOS using SiGe MOSFETs. Actually, a strong concern on SiGe pFETs is the relatively high interface trap density (Dit) at SiGe MOS interfaces, which might be attributed to the undesired GeOx formation in interfacial layers (IL). While the good MOS interface properties by nitridation have been obtained, further reduction in the interface states by oxidation through a GeOx-scavenging process has been reported. Scavenging temperature is crucial to the scavenging process. For high-k materials, Y2O3-based materials is promising for superior SiGe MOS interfaces. In this work, we show the impact of TiN gate electrodes and Post Metal Annealing (PMA) on Dit in TiN/Y2O3/ SiGe gate stacks.