The 79th JSAP Autumn Meeting, 2018

Presentation information

Oral presentation

13 Semiconductors » 13.5 Semiconductor devices and related technologies

[20a-CE-1~12] 13.5 Semiconductor devices and related technologies

Thu. Sep 20, 2018 9:00 AM - 12:15 PM CE (Century Hall)

Takahiro Mori(AIST)

11:45 AM - 12:00 PM

[20a-CE-11] Impact of SiGe Layer Thickness in Starting Substrates on Properties of Ultrathin Body Ge-on-insulator pMOSFETs fabricated by Ge Condensation

〇(DC)KwangWon Jo1, WuKang Kim1, Mitsuru Takenaka1, Takagi Shinichi1 (1.The university of Tokyo)

Keywords:Germanium, GOI, Ge condensation

GOI and SGOI MOSFETs have stirred much attention as p-channel devices, because of the high hole mobility. These structures can provide low leakage current and suppression of short channel effects. Here, strain engineering plays a key factor to enhance the performance of ETB pMOSFET. However, compressive strain (εc) can be easily relaxed in high Ge fractions because of various crystal defects. As a result, it is difficult to achieve high εc in high Ge fractions, where the Ge-like-band structure dominates µh. In order to suppress this strain relaxation, we have proposed a new Ge condensation process including slow cooling. By employing this process, µh of 301 and 138 cm2/Vs was obtained for 15- and 4.5-nm-thick GOI pMOSFETs, respectively, with εc of ~1.5 %. In this work, the resulting strain of GOI films and pMOSFET properties are compared between the SiGe thickness 40 nm and 60 nm in starting substrates in order to mitigate strain relaxation.