The 79th JSAP Autumn Meeting, 2018

Presentation information

Oral presentation

11 Superconductivity » 11.5 Junction and circuit fabrication process, digital applications

[21a-212B-1~11] 11.5 Junction and circuit fabrication process, digital applications

Fri. Sep 21, 2018 9:00 AM - 12:00 PM 212B (212-2)

Masamitsu Tanaka(Nagoya Univ.), Yuki Yamanashi(Yokohama National Univ.)

10:00 AM - 10:15 AM

[21a-212B-5] Design of superconducting LC delay network for adiabatic quantum-flux-parametron logic

Yuxing He1, Naoki Takeuchi1,3, Nobuyuki Yoshikawa1,2 (1.Inst. Adv. Sci., Yokohama Natl. Univ., 2.Dept. of Elec. and Comp. Eng., Yokohama Natl. Univ., 3.JST-PRESTO)

Keywords:delay network, adiabatic quantum-flux-parametron logic, superconducting devices

Adiabatic quantum-flux-parametron (AQFP) logic circuits possess remarkable advantages in energy dissipation. Driven by high frequency AC excitation currents, the clock skews among AQFP logic gates along with the excitation paths are of much importance for correctly functioning the whole system. In this paper, superconducting LC delay network is investigated for AQFP circuits to reduce harmful clock skews for the first time, which may provide considerable benefits for the operation margins of AQFP circuits. Compared with transmission line within the same area, it is noticed that more delay can be provided by the proposed LC network; thus bringing in a considerable size reduction for AQFP logic blocks in the future.