[18p-B201-1~14] 3.15 シリコンフォトニクス

▲ [18p-B201-4] Design Optimization of Ultralow Capacitance InGaAs Waveguide Photodetector on III-V CMOS photonics platform

〇(M2)Pengyuan Cheng¹、Shinichi Takagi¹、Mitsuru Takenaka¹ (1.Univ. of Tokyo)

キーワード：Photodetector, Sub fJ/bit

To reduce the power consumption, the concept of receiver-less PDs was proposed, which requires ultra-low capacitance (<1fF). We have proposed III-V CMOS photonic platform which has uses a III-V on insulator (III-V-OI) wafer. By using the III-V CMOS photonics platform, we have numerically investigated the ultra-low capacitance InGaAs PD with a lateral PIN junction. In this study, we have conducted optimization in the dimensions of the PD to further improve the performance through maximizing the product of light-to-voltage conversion efficiency and 3-dB bandwidth. In our model, InGaAs rib waveguide photodetector with a lateral pin junction is butt-coupled by an a-Si waveguide. In our calculation, ultra-small absorber-volume device with 3 µm length and 170 nm rib height is expected to achieve extreme low power consumption of 0.23 fJ/bit. This study reveals the potential of ultra-low capacitance waveguide InGaAs-OI photodetector and will guide the further fabrication.