[19p-E206-1~19] 3.15 Silicon photonics

[19p-E206-9] Suppression of Vertical Stress at InP/Si Chip-on-Wafer Bonding Interface

〇Takehiko Kikuchi^1,3, Liu Bai³, Takuya Mitarai³, Hideki Yagi¹, Toshiyuki Nitta¹, Masato Furukawa², Tomohiro Amemiya^3,4, Nobuhiko Nishiyama^3,4 (1.TDL, Sumitomo Electric., 2.ATRC, Sumitomo Electric., 3.Tokyo Tech., 4.IIR, Tokyo Tech.)

Keywords:III-V/Si hybrid integration, Plasma activated bonding, Chip-on-wafer bonding

The III-V/Si hybrid integration using direct bonding technologies is very attractive for the realization of a new-generation photonic integrated circuit. In previous work, we have experimentally demonstrated the improvement of bonding strength for the InP/Si chip-on-wafer plasma activated bonding by the tensile strained epitaxial layer grown on the bonding surface of the InP chip. In this presentation, we report the result of theoretical analysis focusing on vertical stress at the bonding interface and figured out the compensation mechanism of vertical stress by the bowing of the InP chip originated from the tensile strain of the epitaxial layer.