17:15 〜 17:30
▲ [12p-B401-16] Effect of High Temperature on Electron Trapping Behavior of GaN HEMTs on SiC Substrates with Field Plate
キーワード：GaN, Electron Trapping, High-electron-mobility transistors
High-electron-mobility transistors (HEMTs) based GaN are excellent candidates for the next-generation power-electronics. However, the dynamic performance of these devices is undermined as operation temperature increases. Due to existence of defects in GaN, electron trapping behavior induces dynamic RON-increase and current collapse at different working temperature. Therefore, it is important to understand the thermal effect of GaN HEMTs. In this work, we investigate the temperature-dependent trapping kinetics in the GaN HEMTs with a field plate on the SiC substrate. The dynamic measurements were carried out from room temperature to ~423K. The results exhibit that the value of RON and the shift of Vth is closely related with the temperature.
Figure 1 shows the variation of Id with Vg (Vd = 6V) of GaN HEMTs with a field plate length of 1 mm at different temperature. In the pulse mode, the quiescent biases of gate and drain (Vgq and Vdq) were set at -10V and 40V, respectively. At room temperature (Figure 1 (a)), the values of the Vth were shifted toward the positive Vg by applying pulsed stress operation, and the ΔVth was estimated as 0.25V. The Vth shift is attributed to carrier injection into the buffer layer under the gate region. The carrier is trapped in deep levels and causes the depletion of 2DEG in channel. Interestingly, when the temperature reached ~373K, the value of the Vth was independent on the bias stress and no change (Figure 1 (b)). The results are indicative that the electron injection and capture was confined at high temperature. And, it is probable that the depletion of 2DEG under the gate region was not changed by off-stress.
Figure 1 shows the variation of Id with Vg (Vd = 6V) of GaN HEMTs with a field plate length of 1 mm at different temperature. In the pulse mode, the quiescent biases of gate and drain (Vgq and Vdq) were set at -10V and 40V, respectively. At room temperature (Figure 1 (a)), the values of the Vth were shifted toward the positive Vg by applying pulsed stress operation, and the ΔVth was estimated as 0.25V. The Vth shift is attributed to carrier injection into the buffer layer under the gate region. The carrier is trapped in deep levels and causes the depletion of 2DEG in channel. Interestingly, when the temperature reached ~373K, the value of the Vth was independent on the bias stress and no change (Figure 1 (b)). The results are indicative that the electron injection and capture was confined at high temperature. And, it is probable that the depletion of 2DEG under the gate region was not changed by off-stress.