[12p-N304-1~14] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[12p-N304-5] Design and analysis of ultralow-voltage-retention Flip-Flop configured with bulk devices

〇Tsubasa Matsuzaki¹, Yusaku Shiotsu¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech.)

Keywords:power gating, flip flop, bulk device