[17a-Z26-1~9] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[17a-Z26-6] Power-gating performance of caches using ultralow-voltage-retention SRAM

〇Hayato Yoshida¹, Yusaku Shiotsu¹, Shuu'ichiro Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech)

Keywords:Power gating, SRAM, Low static power