[20a-P07-1~3] 13.1 Fundamental properties, surface and interface, and simulations of Si related materials

[20a-P07-2] Development of a low computational load simulation model for tunnel field effect transistors using two-dimensional materials and its linkage with circuit simulation

〇Kosuke Yamaguchi¹, Satofumi Souma¹ (1.Kobe Univ.)

Keywords:Phosphorene, TFET, circuit

We will develop a method to simulate the electrical conduction of tunnel field effect transistors (TFETs) using phospholene as the channel material that reduces the computational load while maintaining the accuracy of the simulation. We will also discuss the behavior and characteristics of TFETs when employed as elements in CMOS logic circuits, and what advantages and problems exist in their integration.