[20p-B101-1~12] 10.3 スピンデバイス・磁気メモリ・ストレージ技術

[20p-B101-3] Prospect of pitch scaling for highly dense STT-MRAM with ultra-small magnetic tunnel junctions

〇篠田 峻伸^1,2、五十嵐 純太^1,2,3、陣内 佛霖⁴、深見 俊輔^1,2,4,5,6,7、大野 英男^1,4,5,6 (1.東北大学 電気通信研究所、2.東北大工、3.ロレーヌ大学 Jean Lamour 研究所、4.東北大学材料科学高等研究所、5.東北大学 先端スピントロニクス研究開発センター、6.東北大学 国際集積エレクトロニクス研究開発センター、7.稲盛科学研究機構)

キーワード：STT-MRAM、磁気トンネル接合

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) with magnetic tunnel junctions (MTJs) has been introduced into the market for use as non-volatile memory. So far, we have shown scaling of MTJs down to 2.0 nm while maintaining high performance. For high-density STT-MRAMs, such ultra-small MTJs need to be densely packed with tight pitches, where magnetostatic interferences from neighboring bits may affect device properties. However, only a few of study based on micromagnetic simulation is available to date. Here, we study the interference from neighboring bits in an ultra-small MTJ with various structures through a calculation of stray fields and experimental measurements of the MTJ properties under magnetic fields. We prepare the MTJs with multiple CoFeB/MgO interfaces, which show high retention property and fast switching capability at single-digit-nm range. We first calculate stray fields from neighboring bits with various MTJ stack structures, sizes, and pitches. We then measure the external magnetic field dependence of switching voltage in single-digit-nm MTJs to evaluate their tolerance against the external magnetic field. Combining the calculation and experimental results, we estimate the highest density that can be obtained with the acceptable interference from neighboring bits and find that STT-MRAM using the ultra-small (10-nm) MTJs have the potential to achieve about 100 Gbit/cm2.