2022年第83回応用物理学会秋季学術講演会

講演情報

一般セッション(口頭講演)

10 スピントロニクス・マグネティクス » 10.2 スピン基盤技術・萌芽的デバイス技術

[22a-A205-1~11] 10.2 スピン基盤技術・萌芽的デバイス技術

2022年9月22日(木) 09:00 〜 12:00 A205 (A205)

谷口 知大(産総研)、軽部 修太郎(東北大)

11:30 〜 11:45

[22a-A205-10] Magnonic cross-bar interference-based reconfigurable logic gate

〇(DC)shamim sarker1、Lihao Yao1、Kaijie Ma1、Hiroyasu Yamahara1、Siyi Tang1、Kenyu Terao1、Zhiqiang Liao1、Munetoshi Seki1、Hitoshi Tabata1 (1.Tokyo Univ)

キーワード:Spin wave, Interference, XOR/XNOR

In this study, we demonstrate a reconfigurable XNOR/XOR logic gate based on the interference of the two different types of spin waves (i.e., magnetostatic surface spin waves (MSSWs) and backward volume magnetostatic spin waves (BVMSWs)) propagating along the orthogonal arms. The reconfigurability has been addressed by the current induced temperature rise and thermal gradient. Using the PLD technique, we grew a 90-nm-thick Y3Fe5O12 (YIG) thin film on a Gd3Ga5O12 substrate. In the next step, laser-lithography and wet etching with hot phosphoric acid at 140 0C to fabricate a cross structure. Several alignment exposures were performed to fabricate Pt heater and contact electrodes along with the coplanar waveguides (CPWs), shown in Figure 1(c). Two antennas (i.e., identified as CPW1 and CPW3) were used for SWs excitation, while the CPW2 was used for SWs detection. MSSW from CPW3 and BVMSW from CPW1 interact at the cross junction CPW2 and is detected thereafter. The phase of BVMSW SW is fixed, whereas the phase of the MSSW SWs was tuned from 00 to 3600 to make them interfere constructively and destructively. Figure 1(b)) depicts the interference pattern of the magnetic cross with the application of Jdc =0, 4.5, 6.0, 7.5, 9.0, 9.7, 10.5 GAm-2, represented by the corresponding colors. The change in the interference pattern is caused by the cross interaction of the BVMSW and MSSWdue to the temperature change, as depicted in Figure 1(c). The wavelength shift due to temperature results in the interference pattern shift resulting in the reconfigurability of the logic gate as mentioned in Table-I and Table-II based on the black and green curves, respectively.