[23p-E307-1~20] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

[23p-E307-6] Power-gating performance and architecture of ultralow-voltage-retention SRAM

〇Hiroki Yano¹, Yusaku Shiotsu¹, Shuu'ichirou Yamamoto¹, Satoshi Sugahara¹ (1.FIRST, Tokyo Inst. of Tech)

Keywords:Power-gating