[25p-E307-1~15] 13.5 Semiconductor devices/ Interconnect/ Integration technologies

▲ [25p-E307-10] Improvement of time-lag method applied on Cu diffusion barrier properties evaluation of ultra-thin PVD-Co(W)

〇Yubin DENG¹, Momoko Deura¹, Takeshi Momose¹, Akira Matsuo², Nobuo Yamaguchi², Yukihiro Shimogaki¹ (1.The Univ. of Tokyo, 2.CANON ANELVA CORPORATION)

Keywords:Barrier property, time-lag method, Cu diffusion

With ongoing downsizing of ultra large scale integration (ULSI), currently 5-nm node, Cu interconnects require a liner/barrier layer with lower resistance, better barrier properties, and higher adhesion to Cu than current Ta/TaN bilayer to address the electromigration (EM), stress-induced voiding (SIV), and resistance-capacitive (RC) signal delay. Recently, many alloys have been evaluated as alternative materials as a single-layer barrier/liner that functions as both layers, such as WN, RuTa, MoS₂, CoMo, CoTi, Cu(Mn), etc. Previously, we screened Co(W) is a promising candidate material as a single barrier/liner layer with good performance as mentioned above. As for barrier properties, it is normally evaluated by some qualitative method, like resistance variation test, Cu silicide formation test, Cu diffusion distribution (depth-profiling) measurement and etch-pit test, etc. However, the barrier property of such ultra-thin barrier layer against Cu diffusion, represented by Cu diffusivity (D) in it, has hardly been quantitatively evaluated due to lack of measurement technology. Therefore, we previously proposed the time-lag method to evaluate D of Cu in 5~11-nm-thick PVD-Co(W) film. Here, the time-lag method was modified to improved accuracy on D evaluation, and which was successfully applied to evaluate D of Cu in 1-nm-thick PVD-Co(W) film.