[B4L-D] S5.4-2

[B4L-D-05] An Active Charge Balancer Towards CMOS Integration of an Array of Neural Stimulators

*Seiichi Bun¹, Kota Ando¹, Megumi Akai-Kasaya², Tetsuya Asai¹ (1. Hokkaido University, 2. Hokkaido University and Osaka University)

キーワード：CMOS, neural stimulator, low power consumption, integrated circuit