Schedule 2 1:15 PM - 2:45 PM [IP-P-06] FPGA Implementation of High-Speed LED Display System for Single-Pixel Imaging *Shogo Morita1, Kojiro Matsushita1, Akinori Tsuji2, Hirotsugu Yamamoto1,3 (1. Utsunomiya Univ., 2. Tokushima Univ., 3. JST, ACCEL)
