[P-01] Performance Improvement of Single-Electron Reservoir Computing Circuit with Multiple-Tunnel-Junction Single Electron Oscillator

*Shunya Watanabe¹, Takahide Oya¹ (1. Yokohama National Univ. (Japan))

[P-02] Single-Electron Information-Processing Circuit Inspired by Principles of Molecular Computing

*Kairi Yokoyama¹, Takahide Oya¹ (1. Yokohama National Univ. (Japan))

[P-03] Logically Synthesized Invertible Logic Based on Many-body Effects with Probabilistic-bit Implementation

*Yihan He¹, Chao Fang¹, Sheng Luo¹, Gengchiau Liang¹ (1. National Univ. of Singapore (Singapore))

[P-04] Influence of Weight Transfer Error on Vector-Matrix Multiplication Using AND Array Architectures

*Junsu Yu¹, Donghyun Ryu¹, Taejin Jang¹, Woo Young Choi¹ (1. Seoul National Univ. (Korea))

[P-05] Experimental Demonstration of Memristor Delay-Based Logic In-Memory Ternary Neural Network

Adrien Renaudineau¹, Kamel-Eddine Harabi¹, Clément Turck¹, Axel Laborieux¹, Elisa Vianello², Marc Boquet³, Jean-Michel Portal³, *Damien Querlioz¹ (1. Univ. Paris-Saclay, CNRS, C2N (France), 2. CEA-LETI, Univ. Grenoble-Alpes (France), 3. Aix-Marseille Univ., CNRS, IM2NP (France))

[P-06] A Crossbar-wise IR-drop Compensation Schemes for 5G/6G Hybrid Precoding with Highly-parallel Analog RRAM Array

*Qi Qin¹, Qingtian Zhang¹, Bin Gao¹, Jianshi Tang¹, He Qian¹, Huaqiang Wu¹ (1. Tsinghua Univ. (China))

[P-07] Ultra-Large Memory Window of 3.8V and 75% Read/Write Speed Improvement through Stressed Alumina and Angstrom-Laminated HfZrO2

*Zi-Rong Huang¹, Sheng Min Wang¹, Cheng Rui Liu¹, Yu Ting Chen¹, Yu Tzu Cai¹, Zheng Kai Chen¹, Chia Shou Pai¹, Ying Tsan Tang¹ (1. National Central Univ. (Taiwan))

[P-08] Optimization of Ferroelectricity in Al-Doped HfO₂ Capacitors: Electrical and Endurance Characteristics

*Dong Ru Hsieh¹, Huai En Luo¹, Jia Chian Ni¹, Zi Yang Hong¹, Yi Hsiu Chen¹, Wei Ju Yeh¹, Tien Sheng Chao¹ (1. National Yang Ming Chiao Tung Univ. (Taiwan))

[P-09] Improved Switching behaviors of MFM Capacitor with Reduced E_c and Enhanced P_r-V Linearity by Using La-Al co-doped HfO₂ Ferroelectric layer

*Xujin Song¹, Haolin Li¹, Zhuohua Tang¹, Peng Huang¹, Xiaoyan Liu¹, Jinfeng Kang¹ (1. Peking Univ. (China))

[P-10] Variability Analysis of Stacked-Nanosheet FeFET for MLC Memory and Synapse Applications

*Heng Li Lin¹, Pin Su¹ (1. Univ. of National Yang Ming Chiao Tung (Taiwan))

[P-11] New Understanding of Memory Window Reduction Induced by Ferroelectric Dynamics for HfO₂-based 1T1C FeRAM

*Zhiyuan Fu¹, Mengxuan Yang¹, Kaifeng Wang¹, Qianqian Huang^1,2,3, Ru Huang^1,2 (1. Peking Univ. (China), 2. Beijing Advanced Innovation Center for Integrated Circuits (China), 3. Beijing Superstring Academy of Memory Tech. (China))

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[P-12] Impact of Fringing Field on the Memory Window of FeFET

*Athira Sunil¹, Maximilian Lederer¹, Yannick Raffel¹, Franz Müller¹, Konrad Seidel¹, Thomas Kämpfe¹, Sourav De¹ (1. Fraunhofer Institute for Photonic Microsystems (Germany))

[P-13] Impact of Si-Based Interfacial Layer for Ferroelectric Memory

*Siddheswar Maikap^1,2, Asim Senapati¹, Zhao-Feng Lou³, Min-Hung Lee³ (1. Chang Gung Univ. (Taiwan), 2. Keelung Chang Gung Memorial Hospital (Taiwan), 3. National Taiwan Normal Univ. (Taiwan))

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[P-14] A Comprehensive Understanding for AFeFET with Double Hysteresis Loop Model: Guidelines for Performance and Reliability

*Min Liao¹, Junshuai Chai¹, Jinjuan Xiang², Kai Han³, Yanrong Wang⁴, Hao Xu¹, Xiaolei Wang¹, Jing Zhang⁴, Wenwu Wang¹ (1. Inst. of Microelectronics Chinese Academy of Sciences (China), 2. Beijing Superstring Academy of Memory Tech. (China), 3. Weifang Univ. (China), 4. North China Univ.of Tech. (China))

[P-15] In-Solution Germanium Selenide Nanosheets as Charge Trapping Layer in Flash Memories

*Bashayr Ali Alqahtani¹, Nazek El-Atab¹ (1. Program of Electrical and Computer Engineering, King Abdullah Univ. of Sci. and Tech. (Saudi Arabia))

[P-16] Spherical Shallow Trench Isolation with silicon nitride layer in Buried Gate DRAM for reducing pass gate disturbance

*YeonSeok Kim^1,2, ChangYoung Lim^1,2, MinWoo Kwon^1,2 (1. National Univ. of Gangneung-Wonju (Korea), 2. Lab. of ISDL (Korea))

[P-17] A Physics-based Numerical Model of Resistive Switching Behavior in Electrochemical Metallization Memristor

*Yeongkwon Kim¹ (1. Kyungpook Nat'l Univ. (Korea))

[P-18] A High-Speed and Self-calibratable True Random Number Generator (TRNG) based on Unified Selector-RRAM

*Yabo Qin¹, Zongwei Wang^1,2, Jiajun Gao¹, Linbo Shan¹, Qishen Wang¹, Yimao Cai^1,2, Ru Huang^1,2 (1. Peking Univ. (China), 2. Beijing Adv. Innovation Center for IC (China))

[P-19] Generative Network Utilizing Random Number Based on Memristor Array for Medical Image Synthesis

*Namju Kim¹, Byung Chul Jang¹ (1. Kyungpook Nat. Univ. (Korea))

[P-20] Design of New Single-Electron Reaction-Diffusion Circuit with Ability to Generate and Control Plane Waves

*Keiichiro Tamura¹, Yuito Nakamori¹, Takahide Oya¹ (1. Yokohama National Univ. (Japan))

[P-21] "Theoretical Study of High Performance Germanium Nanowire Quantum Dot"

*Han-Wei Yang¹, Yung-Feng Wu¹, Ming-Jung Hsu¹, Shao-Chen Lee¹, Ying-Tsan Tang¹ (1. National Central University (Taiwan))

[P-22] Enhanced Electrical Performance of Ge nMOSFET with Rapid Remote Plasma Oxidation Treatment

*Jia-Cheng Liu¹, Dun-Bao Ruan², Kuei-Shu Chang-Liao¹, Guan-Ting Liu¹ (1. National Tsing Hua University (Taiwan), 2. Fuzhou University (China))

[P-23] Improved Radiation Hardness for Nanosheet FETs with Partial Bottom Dielectric Isolation

*Xun-Ting Zheng¹, Vita Pi-Ho Hu¹ (1. National Taiwan University (Taiwan))

[P-24] Phosphorus Deactivation and Electron Mobility Enhancement in Ultrathin Silicon Nanosheets

*Michele Perego¹, Andrea Pulici^1,2, Stefano Kuschlan^1,3, Gabriele Seguini¹, Fabiana Taglietti², Marco Fanciulli^2,1, Riccardo Chiarcos³, Michele Laus³ (1. CNR-IMM Unit of Agrate (Italy), 2. Università degli Studi di Milano-Bicocca (Italy), 3. Università del Piemonte Orientale ‘‘A. Avogadro’’ (Italy))

[P-25] Performance Investigation of Source/Drain Extension Region on Nanosheet FET: A Digital Design Perspective

*Shobhit Srivastava¹, Sourabh Panwar¹, Shashidhara M.¹, Navjeet Bagga², Deepak Joshi¹, Abhishek Acharya¹ (1. Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat (India), 2. IIT Bhubaneswar, Odisha (India))

[P-26] Comprehensive Investigation of Back Gate Biasing on Performance of Line TFETs

*Sourabh Panwar¹, Shobhit Srivastava¹, Shashidhara M¹, Prabhat Dubey², Deepak Joshi¹, Abhishek Acharya¹ (1. Sardar Vallabhbhai National Institute of Technology, SVNIT (India), 2. Univ. of Pisa (Italy))

[P-27] Atomically Thin 0.65nm and 6nm Vertical Side-Wall MoS₂Channel Transistors

*Kihan Kim¹, Byungchul Jang¹ (1. Kyungpook National Univ. (Korea))

セッション情報

[P] Poster session