2017 International Conference on Solid State Devices and Materials

Awards

Awards

There are three categories of awards for authors who presented papers at the SSDM: SSDM Award, SSDM Paper Award, and SSDM Young Researcher Award. The SSDM Award will be presented to researchers who contributed an outstanding paper at past SSDM. The Award Committee selects this award. The SSDM Paper Award will be presented to authors who presented the best paper at the previous year's SSDM. The SSDM Young Researcher Award will be given to a few young researchers, not older than thirty, who presented excellent papers at the previous year's SSDM. The SSDM Paper Award and the SSDM Young Researcher Award are nominated by the Program Committee and decided by the Organizing Committee.
 
SSDM2017 presents the SSDM Award to an outstanding paper; Takatomo Enoki, Yohtaro Umeda and Yasunobu Ishii, of NTT LSI Laboratories for the presentation of the paper entitled "0.05-µm-Gate InAlAs/InGaAs HEMT and Reduction of Its Short-Channel Effects" presented as paper No. D-9-4 at the SSDM1993, held in Makuhari.
 
The SSDM Paper Award is presented to Thomas Ferrotti, Blampey Benjamin, Duprez Hélène, Jany Christophe, Chantre Alain, Frederic Boeuf, Seassal Christian and Ben Bakir Badhise for a paper entitled "1.3µm Hybrid III-V on Silicon Transmitter Operating at 25Gb/s" which was presented at the SSDM2016 held in Tsukuba.
 
The SSDM Young Researcher Award is given to four researchers: (1) Hiroki Shirakawa, who presented a paper entitled "Multi-level Operation of a High-speed, Low Power Topological Switching Random-access Memory (TRAM) Based on a Ge Deficient GexTe/Sb2Te3 Superlattice"; (2) Thilo Werner, who presented a paper entitled " Exploitation of RRAM Variability to Improve On-line Unsupervised Learning in Small-scale Spiking Neural Networks"; (3) Shoichi Nishitani, who presented a paper entitled "Development of Molecularly Imprinted Polymer-Gate Field Effect Transistor for Sugar Chain Sensing"; (4) Masayuki Ishitaki, who presented a paper entitled "Experimental Demonstration of a Josephson Junction under Spin Current Injection".
 

Awards in the SSDM2017
SSDM Award

"0.05-µm-Gate InAlAs/InGaAs HEMT and Reduction of Its Short-Channel Effects"
Takatomo Enoki, Yohtaro Umeda and Yasunobu Ishii
NTT LSI Laboratories
Presentation No. D-9-04, presented at the 25th International Conference on Solid State Devices and Materials (1993), Makuhari.
 
In this paper, how the world's top-level high-frequency characteristics were achieved through the development of a lattice-matched InAlAs/InGaAs high-electron-mobility transistor (HEMT) on an InP substrate with a T-shaped gate was described. The design guidelines based on systematic investigations of the short-channel device structure were also presented.
In the early 1990s when this paper was published, the InAlAs/InGaAs HEMT on an InP substrate was expected to become a key device in 40 Gbps optical communications systems or millimeter-wave wireless communications. This is because it had promising high-speed/high-frequency characteristics that surpassed those of Si or GaAs devices. Thus, to improve these characteristics, the scaling down of the device was intensively studied. It was reported that the high-frequency characteristics required for a 40 Gbps optical communications system could be achieved by using a pseudomorphic InAlAs/InGaAs HEMT on an InP substrate with a gate length reduced by 0.05 μm. However, the breakdown voltage of this pseudomorphic HEMT was low. Therefore, the application of the device was severely limited, and it was difficult to apply it to the logic circuits of 40 Gbps optical communications systems.
In this paper, the fabrication of lattice-matched InAlAs/InGaAs HEMTs on an InP substrate with excellent breakdown voltage characteristics and gate lengths of 0.5 to 0.05 μm, and the systematic investigation of the immunity to the short-channel effect with respect to the design of the channel layer and the barrier layer were reported. Consequently, the use of a lattice-matched HEMT with a gate length of 0.05 μm was found to result in a current gain cutoff frequency of 300 GHz and a maximum oscillation frequency of 235 GHz, which are comparable to those of pseudomorphic HEMTs.
Since the device technology reported in this paper demonstrated that both breakdown voltage and high-frequency characteristics can be attained simultaneously, it has been used as a basic technology of integrated circuits for optical communications and opened the door to the practical application of 40 Gbps optical communications.
On the basis of the above, the great contribution of this paper to industry and academia is recognized. We here present this SSDM Award in honor of its value.
 

Takatomo Enoki

NTT Electronics Corporation

Takatomo Enoki received M.S. degrees in physics and Dr. Eng. degree in electrical engineering from the Tokyo Institute of Technology in 1984 and 1996, respectively.

In 1984, he joined the Atsugi Electrical Communications Laboratories of NTT. Since then, he has been engaged in R&D on fabrication technologies for high-frequency and high-speed integration circuits using compound semiconductors for optical and wireless communications systems.

After serving as a director of Photonics Laboratories at NTT, he moved to NTT Electronics Corp. as a senior vice president of the broadband system & device business group in 2012 and is developing compound semiconductor devices for communications systems.

He is a fellow of the IEEE and the IEICE.

 

Yohtaro Umeda

Tokyo University of Science

Yohtaro Umeda received the B.S. and M.S. degrees in physics and the Ph.D. degree in electrical engineering from the University of Tokyo, Tokyo, Japan, in 1982, 1984, and 2000, respectively. In 1984, he joined Nippon Telegraph and Telephone (NTT) Corporation and engaged in high-speed circuit application of GaAs MESFETs and InP HEMTs. He moved to Tokyo University of Science, Chiba, Japan, as a professor, where he is engaged in the study of high-speed analog/digital circuits and signal processing for radio and optical communication systems. He is a member of the JSAP, IEICE, and IEEE.

 

Yasunobu Ishii

ISHII P.E.Jp Office

Yasunobu Ishii was born in Fukuoka Prefecture, Japan, on 19 June, 1950. He received the B.E., M.E., and D.E. degrees in electronics from Osaka University, Japan, in 1973, 1975, and 1984, respectively. In 1975, he joined the Electrical Communication Laboratories, NTT, Tokyo, Japan, where he has been engaged in research on GaAs FETs and ICs. From 1983 to 2000,he was with NTT Atsugi Laboratories where he conducted research on InP-based heterostructure electron devices. In 2001, he joined NTT Electronics Corp., to establish 6” GaAs IC production line. In 2003 he resigned from NTT group, and joined Yokowo Co., ltd., where he has engaged in millimeter-wave devices for the automotive radars. From 2014, he has engaged in engineering consultant at ISHII P.E.Jp Office in Yokohama as a certificated Professional Engineer of Japan.

 

SSDM Paper Award

Presentation No. C-3-02

"1.3µm Hybrid III-V on Silicon Transmitter Operating at 25Gb/s "

Thomas Ferrotti

STMicroelectronics

Thomas Ferrotti received both his M.S and Engineering degrees in Micro- and Nano-technologies for Integrated Systems from Grenoble Institute of Technology (France) in 2012, in collaboration with Politecnico di Torino (Italy) and Ecole Polytechique Fédérale de Lausanne (Switzerland).

He received his Ph. D. degree of electronics, micro- and nano-electronics, optics and laser from the Université de Lyon (France) in 2016, in partnership with both CEA-LETI (Grenoble, France) and STmicroelectronics (Crolles, France). His Ph. D. work was mainly focused on the design, fabrication and characterization of a hybrid III-V on silicon transmitter for high-speed communications.

He is currently working as a process integration engineer at STMicroelectronics (Crolles, France). His work is now centered on the R&D of CMOS image sensors.

 

Frederic Boeuf

STMicroelectronics

Frédéric Boeuf, born 1972, obtained his M.Eng. and M.Sc. degree from Institut National Polytechnique de Grenoble in 1996 and Ph.D. from the University Joseph Fourier of Grenoble (France) in 2000. Then he joined STMicroelectronics working on Advanced Devices Physics and Integration and lead the preliminary work for 65nm to 20nm CMOS nodes.. He was deeply involved into the development of the MASTAR model used by the ITRS to create the CMOS roadmap, and in 2012 he was a co-recipient of the General Ferié Grand Prize for his work on the FDSOI technology. He authored and co-authored over 190 technical papers. He is currently managing the Silicon Photonics and Advanced Devices Technology group inside STMicroelectonics Silicon Technology Development department and joined the University of Tokyo as JSPS invited fellow from august 2016 to june 2017.

 

Ben Bakir Badhise

CEA-LETI

Dr. Badhise Ben Bakir received the Master’s degree in Physics from Université Claude Bernard, Lyon, France, in 2003, and the PhD degree in Optical and Electrical engineering from Ecole Centrale de Lyon, Ecully, France, in 2006. In 2007, he joined the Optronics Department, at CEA Leti. He is the author and coauthor of more than 120 papers in international journals and conferences. He holds 22 patents. His current research interests include physics of optoelectronic devices and nanostructures, micro-nano-fabrication related to Si and III–V based materials for hybrid optical integrated circuits. Since 2017, he is also in charge of semiconductor integration and optical engineering of wavelength-scale pixels for visible light communications, display and lighting applications.

 

SSDM Young Researcher Award

Presentation No. B-3-05

"Multi-level Operation of a High-speed, Low Power Topological Switching Random-access Memory (TRAM) Based on a Ge Deficient GexTe/Sb2Te3 Superlattice"

Hiroki Shirakawa

Nagoya University

He received the B.S. and M.S. degrees in Science from University of Tsukuba in 2013 and 2015, respectively. He is currently a Ph.D student with Nagoya University. His research interests are semiconductor memories such as conductive bridge memories, phase change memories, and charge trap memories.

 
Presentation B-7-05

"Exploitation of RRAM Variability to Improve On-line Unsupervised Learning in Small-scale Spiking Neural Networks"

Thilo Werner

CEA-Leti

Thilo Werner received the B.Sc. and M.Sc. degrees in Electronic and Sensor Materials from TU Bergakademie Freiberg, Freiberg, Germany and imec Belgium, Leuven, Belgium in 2010 and 2013, respectively. He is currently pursuing a Ph.D. program with CEA-Leti, Grenoble, France and Universite Grenoble Alpes, Grenoble, France. His current research interests include the characterization and understanding of emerging nonvolatile memory technologies for the implementation of innovative neuromorphic computing systems.

 
Presentation No. H-2-02

"Development of Molecularly Imprinted Polymer-Gate Field Effect Transistor for Sugar Chain Sensing"

Shoichi Nishitani

The University of Tokyo

Education
Department of Materials Engineering, The University of Tokyo
Undergraduate, Materials Engineering (2014-2015), Tokyo, Japan

Department of Materials Engineering, The University of Tokyo
Master, Materials Engineering (2015-2017), Tokyo, Japan

Research Field
Field-effect transistor biosensor

 
Presentation No. G-4-02

"Experimental Demonstration of a Josephson Junction under Spin Current Injection"

Masayuki Ishitaki

Kyushu University

Mr. Masayuki Ishitaki was received the B.A. degree in physics from Kyushu University, Fukuoka, Japan, in 2012.

He is now a master course student of Kyushu University. His research interest includes conversion of Cooper pairs in ferromagnet/superconductor hybrid nano-structures.