Oral Presentation

01: Advanced CMOS: Material Fundamentals / Process Science / Device Physics

[G-10] Advanced CMOS: Device, Process and Material

Thu. Sep 29, 2022 4:00 PM - 6:00 PM 301 (3F)

Session Chair: Nobuyuki Mise (Hitachi High-Tech Corp.), Keisuke Yamamoto (Kyushu Univ.)

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4:00 PM - 4:30 PM

[G-10-01 (Invited)] Design-Technology Co-Optimization for Future CMOS:
from finFET to CFETs and Backside Power

Geert Hellings¹, Pieter Schuddinck¹, Samantha Liu¹, Shairfe Muhammad Salahuddin¹, Gioele Mirabelli¹, Rongmei Chen¹, Anabela Veloso¹, Anne Jourdain¹, 〇Gaspard Hiblot¹, Naoto Horiguchi¹, Julien Ryckaert¹ (1. imec (Belgium))

Presentation style: Online

4:30 PM - 4:45 PM

[G-10-02] Impact of Back-side Power Delivery Network Layout on the FinFET Device Performance

Goutham Arutchelvan¹, Thomas Chiarella¹, Hiroaki Arimura¹, Anabela Veloso¹, Anne Jourdain¹, Eugenio Dentoni Litta¹, Naoto Horiguchi¹, 〇Jerome Mitard¹ (1. imec (Belgium))

Presentation style: On-site (in-person)

4:45 PM - 5:00 PM

[G-10-03] Investigation of access resistance components in Si-channel p-FinFET using cascaded devices.

〇Pierre Eyben¹, Goutham Arutchelvan¹, Thomas Chiarella¹, Hiroaki Arimura¹, Romain Ritzenthaler¹, Jérome Mitard¹, Eugenio Dentoni Litta ¹, Naoto Horiguchi¹, Ludovic Goux¹ (1. Imec (Belgium))

Presentation style: On-site (in-person)

5:00 PM - 5:15 PM

[G-10-04] Impacts of Annealing Temperature and Atmosphere on (111) and (100) n-Ge MOS Interface Properties with Plasma Oxidation GeO_x and ALD Al₂O₃

〇Xueyang Han¹, Chia-Tsong Chen¹, Mengnan Ke², Ziqiang Zhao¹, Kasidit Toprasertpong¹, Mitsuru Takenaka¹, Shinichi Takagi¹ (1. Univ. of Tokyo (Japan), 2. Chiba Univ. (Japan))

Presentation style: On-site (in-person)

5:15 PM - 5:30 PM

[G-10-05] Low Temperature Selective Growth of Ga-Doped Germanium Source / Drain for pMOS Devices

〇Clement Porret¹, Gianluca Rengo^1,2,3, Mustafa Ayyad¹, Andriy Hikavyy¹, Erik Rosseel¹, Robert Langer¹, Roger Loo¹ (1. imec vzw (Belgium), 2. Quantum Solid State Physics, KU Leuven (Belgium), 3. FWO - Vlaanderen (Belgium))

Presentation style: On-site (in-person)

5:30 PM - 5:45 PM

[G-10-06] Atomic Layer Etching of Ti-Compounds: Mechanism and Etch Selectivity Control for Advanced Device Fabrication

Bablu Mukherjee^1,2, René H.J. Vervuurt³, Airah Peraro Osonio², 〇Takayoshi Tsutsumi², Masaru Hori², Nobuyoshi Kobayashi² (1. ASM Japan K.K. (Japan), 2. Nagoya Univ. (Japan), 3. ASM Belgium (Belgium))

Presentation style: Online

5:45 PM - 6:00 PM

[G-10-07] Super-conformal CVD Ruthenium with 1 Angstrom Liner in Advanced MOL Local Interconnect

〇Maryamsadat Hosseini¹, Alicja Leśniewska¹, Gyana Pattanaik², Robert Clark², Anish Dangol¹, Marleen H van der Veen¹, Nicolas Jourdan¹, Gert Leusink², Hunter Frost², Cory Wajda², Eugenio Dentoni Litta¹, Naoto Horiguchi¹ (1. imec (Belgium), 2. TEL (United States of America))

Presentation style: On-site (in-person)

Session information

[G-10] Advanced CMOS: Device, Process and Material

[G-10-01 (Invited)] Design-Technology Co-Optimization for Future CMOS:
from finFET to CFETs and Backside Power

[G-10-02] Impact of Back-side Power Delivery Network Layout on the FinFET Device Performance

[G-10-03] Investigation of access resistance components in Si-channel p-FinFET using cascaded devices.

[G-10-04] Impacts of Annealing Temperature and Atmosphere on (111) and (100) n-Ge MOS Interface Properties with Plasma Oxidation GeO_x and ALD Al₂O₃

[G-10-05] Low Temperature Selective Growth of Ga-Doped Germanium Source / Drain for pMOS Devices

[G-10-06] Atomic Layer Etching of Ti-Compounds: Mechanism and Etch Selectivity Control for Advanced Device Fabrication

[G-10-07] Super-conformal CVD Ruthenium with 1 Angstrom Liner in Advanced MOL Local Interconnect

Authentication

Session information

[G-10] Advanced CMOS: Device, Process and Material

[G-10-01 (Invited)] Design-Technology Co-Optimization for Future CMOS:from finFET to CFETs and Backside Power

[G-10-02] Impact of Back-side Power Delivery Network Layout on the FinFET Device Performance

[G-10-03] Investigation of access resistance components in Si-channel p-FinFET using cascaded devices.

[G-10-04] Impacts of Annealing Temperature and Atmosphere on (111) and (100) n-Ge MOS Interface Properties with Plasma Oxidation GeOx and ALD Al2O3

[G-10-05] Low Temperature Selective Growth of Ga-Doped Germanium Source / Drain for pMOS Devices

[G-10-06] Atomic Layer Etching of Ti-Compounds: Mechanism and Etch Selectivity Control for Advanced Device Fabrication

[G-10-07] Super-conformal CVD Ruthenium with 1 Angstrom Liner in Advanced MOL Local Interconnect

Authentication

[G-10-01 (Invited)] Design-Technology Co-Optimization for Future CMOS:
from finFET to CFETs and Backside Power

[G-10-04] Impacts of Annealing Temperature and Atmosphere on (111) and (100) n-Ge MOS Interface Properties with Plasma Oxidation GeO_x and ALD Al₂O₃