[F-2] PCM, MRAM, and RRAM

[F-2-01] Study of Write Error Rate in MRAM with Fixed Voltage Input

〇Lihua An¹, Yue Xin¹, Zhengping Yuan¹, Yumeng Yang¹, Zhifeng Zhu¹ (1. ShanghaiTech Univ. (China))

Presentation style: Online

https://doi.org/10.7567/SSDM.2022.F-2-01

The write error rate (WER) is studied in the bit cell driven by a fixed voltage. A new simulation framework is developed to enable the co-simulation of magnetic tunnel junction (MTJ) and transistor. In contrast to the commonly known result, the WER has a significant dependence on the device properties such as the resistance and the area of MTJ. For the devices studied here, the WER decreases from 31% to 3% as the resistance is increased from 1kΩ to 6kΩ, and the WER increases from 31% to 67% when the area is increased from 50nm×50nm to 100nm×100nm. In addition, our results show that the device with a higher resistance-area product can be more attractive when one has a strict requirement on the WER.