[F-7] In-Memory and Unconventional Computing

[F-7-04] A High-Efficiency, Reliable Multilevel Hardware-Accelerated Annealer with In-Memory Spin Coupling and Complementary Read Algorithm

〇Yun-Yuan Wang¹, Yu-Hsuan Lin¹, Dai-Ying Lee¹, Ming-Liang Wei¹, Cheng-Hsien Lu¹, Po-Hao Tseng¹, Ming-Hsiu Lee¹, Kuang-Yeu Hsieh¹, Keh-Chung Wang¹, Chih-Yuan Lu¹ (1. Macronix Int'l Corp., Ltd. (Taiwan))

Presentation style: Online

https://doi.org/10.7567/SSDM.2022.F-7-04

The cost-effective, high-density, and robust floating-gate (FG) spin coupler based on the NOR flash technology is proposed for the first time to overcome the challenges of convergence speed and the capacity limitation in the conventional SRAM-based simulated annealing (SA) machines. In addition, the novel complementary read algorithm can further increase the tolerance on threshold voltage (Vth) variation by 60%. Demonstrations show that the proposed in-memory spin coupling architecture provides high efficiency and scalability in solving the combinatorial problems regardless of the problem size.