Backside power delivery (BSPDN) with Buried Power Rail (BPR) is an essential enabler for CMOS scaling beyond the 5nm node. In this work, we show that integrating BPR and Nano-Through Silicon Via (n-TSV) close to the active channel does not degrade the device performance, thus, confirming that the stress transfer from BSPDN elements is rather weak. Design guidelines with respect to n-TSV proximity and number of VBPR vias for optimized device performance and reduced footprint is discussed.