[A-2] Device Application I: Low Dimensional Devices and Materials

Wed. Sep 6, 2023 4:00 PM - 5:30 PM Room A (131+132, Bldg. 1)

Session Chairs: Mahito Yamamoto (Kansai Univ.), Takeshi Yanagida (Univ. of Tokyo)

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4:00 PM - 4:15 PM

[A-2-01] Er ₂O ₃ top gate MoS ₂ FET with EOT lower than 1 nm

^○Shuhong Li¹, Tomonori Nishimura¹, Kosuke Nagashio¹ (1. Univ. of Tokyo (Japan))

4:15 PM - 4:30 PM

[A-2-02] Thermal-aware Design of Metal Nanosheet Sensors for Low-energy, Highly Sensitive Hydrogen Sulfide Nanoscale Sensors

^○Taro Kato¹, Takahisa Tanaka², Ken Uchida¹ (1. Univ. of Tokyo (Japan), 2. Keio Univ. (Japan))

4:30 PM - 4:45 PM

[A-2-03] Self-Aligned WO _x S/D Contacts to Gate Stacks with TiO _x Nucleation Layer by Multiple-Deposition Method in WSe ₂ pFETs

^○Ryosuke Kajikawa¹, Takamasa Kawanago¹, Iriya Muneta¹, Takuya Hoshii¹, Kuniyuki Kakushima¹, Kazuo Tsutsui¹, Hitoshi Wakabayashi¹ (1. Tokyo Institute of Technology (Japan))

4:45 PM - 5:00 PM

[A-2-04] High-Frequency Semiconductor-Graphene-Semiconductor Transistors Using Epitaxial Graphene

Chi Liu^1,2, ^○Xiaoyue Wang^1,2, Haiyan Jiang^1,2, Xuqi Yang^1,2, Zhongying Xue³, Zengfeng Di³, Dongming Sun^1,2 (1. Inst. of Metal Res., Chinese Academy of Sci. (China), 2. Univ. of Sci. and Tech. of China (China), 3. Shanghai Inst. of Microsystem and Info. Tech., Chinese Academy of Sci. (China))

5:00 PM - 5:15 PM

[A-2-05] High-performance CMOS inverter based on MoTe ₂-FETs achieved by contact doping and channel encapsulation

^○Tianshun Xie¹, Mengnan Ke², Nobuyuki Aoki³ (1. Chiba Univ. (Japan), 2. Chiba Univ. (Japan), 3. Chiba Univ. (Japan))

5:15 PM - 5:30 PM

[A-2-06 (Late News)] Multilevel Storage Enabled by Light Erasable GNDs Floating Gate Transistor with MoS ₂ Channel

^○Han Hsiang Tai¹, Yu Yuan Su¹, Jer Chyi Wang^1,2,3, Wen Hao Chang^4,5, Chao Sung Lai^1,6,7 (1. Department of Electronic Engineering, Chang Gung Univ. (Taiwan), 2. Department of Neurosurgery, Chang Gung Memorial Hospital (Taiwan), 3. Department of Electronic Engineering, Ming Chi Univ. of Tech. (Taiwan), 4. Research Center for Applied Sciences, Academia Sinica (Taiwan), 5. Department of Electrophysics, National Yang Ming Chiao Tung Univ. (Taiwan), 6.Department of Nephrology, Chang Gung Memorial Hospital (Taiwan), 7.Department of Materials Engineering, Ming Chi Univ. of Tech. (Taiwan))

Session information

[A-2] Device Application I: Low Dimensional Devices and Materials

[A-2-01] Er ₂O ₃ top gate MoS ₂ FET with EOT lower than 1 nm

[A-2-02] Thermal-aware Design of Metal Nanosheet Sensors for Low-energy, Highly Sensitive Hydrogen Sulfide Nanoscale Sensors

[A-2-03] Self-Aligned WO _x S/D Contacts to Gate Stacks with TiO _x Nucleation Layer by Multiple-Deposition Method in WSe ₂ pFETs

[A-2-04] High-Frequency Semiconductor-Graphene-Semiconductor Transistors Using Epitaxial Graphene

[A-2-05] High-performance CMOS inverter based on MoTe ₂-FETs achieved by contact doping and channel encapsulation

[A-2-06 (Late News)] Multilevel Storage Enabled by Light Erasable GNDs Floating Gate Transistor with MoS ₂ Channel

Authentication

Session information

[A-2] Device Application I: Low Dimensional Devices and Materials

[A-2-01] Er 2O 3 top gate MoS 2 FET with EOT lower than 1 nm

[A-2-02] Thermal-aware Design of Metal Nanosheet Sensors for Low-energy, Highly Sensitive Hydrogen Sulfide Nanoscale Sensors

[A-2-03] Self-Aligned WO x S/D Contacts to Gate Stacks with TiO x Nucleation Layer by Multiple-Deposition Method in WSe 2 pFETs

[A-2-04] High-Frequency Semiconductor-Graphene-Semiconductor Transistors Using Epitaxial Graphene

[A-2-05] High-performance CMOS inverter based on MoTe 2-FETs achieved by contact doping and channel encapsulation

[A-2-06 (Late News)] Multilevel Storage Enabled by Light Erasable GNDs Floating Gate Transistor with MoS 2 Channel

Authentication

[A-2-01] Er ₂O ₃ top gate MoS ₂ FET with EOT lower than 1 nm

[A-2-03] Self-Aligned WO _x S/D Contacts to Gate Stacks with TiO _x Nucleation Layer by Multiple-Deposition Method in WSe ₂ pFETs

[A-2-05] High-performance CMOS inverter based on MoTe ₂-FETs achieved by contact doping and channel encapsulation

[A-2-06 (Late News)] Multilevel Storage Enabled by Light Erasable GNDs Floating Gate Transistor with MoS ₂ Channel