[A-6] Device Application II: Low Dimensional Devices and Materials

Fri. Sep 8, 2023 10:45 AM - 12:15 PM Room A (131+132, Bldg. 1)

Session Chairs: Satoshi Hiura (Hokkaido Univ.), Toshifumi Irisawa (AIST)

+Add all to schedule

10:45 AM - 11:15 AM

[A-6-01 (Invited)] Efficient Electron Spin Orientation and Nonlinear Spin Response in a Room-Temperature All-Semiconductor Spin Amplifier

^○Yuqing Huang^1,2, Irina A. Buyanova¹, Weimin M. Chen¹ (1. Linköping Univ. (Sweden), 2. Inst. of Semiconductors, Chinese Academy of Sciences (China))

11:15 AM - 11:30 AM

[A-6-02] First Demonstration of Bi-directional Sub-50 mV/dec MoS ₂-Hf _0.5Zr _0.5O ₂ Ferroelectric FET with Record High Memory Window Efficiency Exceeding the Theoretical Limit and High-Precision Analog Synapse

^○HENG XIANG¹, Yu-Chieh Chien¹, Lingqi Li¹, Haofei Zheng¹, Sifan Li¹, Yufei Shi¹, Kah-Wee Ang^1,2 (1. National Univ. of Singapore (Singapore), 2. Inst. of Materials Res. and Eng. (Singapore))

11:30 AM - 11:45 AM

[A-6-03] Heterogeneous Integration of 32 × 32 1S1R Crossbar Array using 2D Hafnium Diselenide on Si Platform and its Compute-in-Memory Hardware Featuring Low Latency and High Energy Efficiency

^○Samarth Jain¹, Sifan Li¹, Jianze Wang¹, Xuanyao Fong¹, Kah-Wee Ang^1,2 (1. National University of Singapore (Singapore), 2. Institute of Materials Research and Engineering, A*STAR (Singapore))

11:45 AM - 12:00 PM

[A-6-04] Artificial Excitatory and Inhibitory Neuron Enabled by a Single Threshold-Switching Double-Gate MoS ₂ Transistor

^○Hanxi Li¹, Jiayang Hu¹, Anzhe Chen¹, Yishu Zhang¹, Yang Xu¹, Bin Yu¹ (1. Zhejiang university (China))

12:00 PM - 12:15 PM

[A-6-05 (Late News)] Ultra Flexible and Highly Integrated All Solid-State Artificial Synapse Arrays Based on van der Waals 2D/Solid Electrolyte Heterostructures for Wearable Edge Computing

^○Yonghun Kim¹ (1. Korea Institute of Materials Science (Korea))

Session information

[A-6] Device Application II: Low Dimensional Devices and Materials

[A-6-01 (Invited)] Efficient Electron Spin Orientation and Nonlinear Spin Response in a Room-Temperature All-Semiconductor Spin Amplifier

[A-6-02] First Demonstration of Bi-directional Sub-50 mV/dec MoS ₂-Hf _0.5Zr _0.5O ₂ Ferroelectric FET with Record High Memory Window Efficiency Exceeding the Theoretical Limit and High-Precision Analog Synapse

[A-6-03] Heterogeneous Integration of 32 × 32 1S1R Crossbar Array using 2D Hafnium Diselenide on Si Platform and its Compute-in-Memory Hardware Featuring Low Latency and High Energy Efficiency

[A-6-04] Artificial Excitatory and Inhibitory Neuron Enabled by a Single Threshold-Switching Double-Gate MoS ₂ Transistor

[A-6-05 (Late News)] Ultra Flexible and Highly Integrated All Solid-State Artificial Synapse Arrays Based on van der Waals 2D/Solid Electrolyte Heterostructures for Wearable Edge Computing

Authentication

Session information

[A-6] Device Application II: Low Dimensional Devices and Materials

[A-6-01 (Invited)] Efficient Electron Spin Orientation and Nonlinear Spin Response in a Room-Temperature All-Semiconductor Spin Amplifier

[A-6-02] First Demonstration of Bi-directional Sub-50 mV/dec MoS 2-Hf 0.5Zr 0.5O 2 Ferroelectric FET with Record High Memory Window Efficiency Exceeding the Theoretical Limit and High-Precision Analog Synapse

[A-6-03] Heterogeneous Integration of 32 × 32 1S1R Crossbar Array using 2D Hafnium Diselenide on Si Platform and its Compute-in-Memory Hardware Featuring Low Latency and High Energy Efficiency

[A-6-04] Artificial Excitatory and Inhibitory Neuron Enabled by a Single Threshold-Switching Double-Gate MoS 2 Transistor

[A-6-05 (Late News)] Ultra Flexible and Highly Integrated All Solid-State Artificial Synapse Arrays Based on van der Waals 2D/Solid Electrolyte Heterostructures for Wearable Edge Computing

Authentication

[A-6-02] First Demonstration of Bi-directional Sub-50 mV/dec MoS ₂-Hf _0.5Zr _0.5O ₂ Ferroelectric FET with Record High Memory Window Efficiency Exceeding the Theoretical Limit and High-Precision Analog Synapse

[A-6-04] Artificial Excitatory and Inhibitory Neuron Enabled by a Single Threshold-Switching Double-Gate MoS ₂ Transistor