[E-3] DRAM

Thu. Sep 7, 2023 9:00 AM - 10:00 AM Room E (223, Bldg. 2)

Session Chairs: E Ray Hsieh (National Central Univ.), Atsushi Himeno (Panasonic Holdings Corporation)

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9:00 AM - 9:15 AM

[E-3-01] Improvement of Cell Transistors in High-k/ Metal-Gate Peripheral Transistors DRAM Technology for High Performance Graphic Memories

^○Dongkyu Jang¹, Jieun Lee¹, Daekyum Kim¹, Kyoungrock Nho¹, Inkyum Lee¹, Shindeuk Kim¹, Taehoon Park¹ (1. Samsung Electronics Corp. (Korea))

9:15 AM - 9:30 AM

[E-3-02] Novel Stacked Gate All-Around Nanosheet Transistor-Based DRAM

^○Imtiyaz Ahmad khan¹, Sanjeev Kumar Manhas¹, Arvind Kumar², Mahendra Pakala² (1. Indian Inst. of Tech. Roorkee (India), 2. Applied Materials Inc. (United States of America))

9:30 AM - 9:45 AM

[E-3-03] Exploring Vertical DRAM Architecture using Advanced Pathfinding Techniques

^○TaeYeon Oh¹ (1. LAM RESEARCH (Korea))

9:45 AM - 10:00 AM

[E-3-04] "A Novel Solution to improve Static and Dynamic Retention Characteristics by Enhancing Hydrogen Passivation with in-situ LD-TEOS/TEOS Dual Layer"

^○JIEUN LEE¹, Dongkyu Jang¹, Inkyum Lee¹, Shindeuk Kim¹, Taehoon Park¹, Hyeongsun Hong¹ (1. Samsung Electronics Corp. (Korea))

Session information