[G-5] Heterogenous Integration for High Performance Computing; System, Material, Process and Chiplet I

Fri. Sep 8, 2023 9:00 AM - 10:15 AM Room G (231, Bldg. 2)

Session Chairs: Takeyasu Saito (Osaka Metropolitan Univ.), François Andrieu (CEA-Leti)

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9:00 AM - 9:30 AM

[G-5-01 (Invited)] EMIB and Advanced Substrate Packaging Technologies to Enable Heterogeneous Integration (HI) Applications

^○Gang Duan¹, Ravi Mahajan¹, Rahul Manepalli¹, Hamid Azimi¹ (1. Intel Corp. (United States of America))

9:30 AM - 9:45 AM

[G-5-02] High-Bendable 3D Corrugated Interconnections for Chiplet-Embedded Flexible Hybrid Electronics Using Wafer-Level Packaging

^○Chang Liu¹, Tadaaki Hoshi¹, Jiayi Shen¹, Atsushi Shinoda¹, Zehua Du¹, Hisashi Kino^1,2, Tetsu Tanaka^1,2, Takafumi Fukushima^1,2 (1. Graduate School of Eng., Tohoku Univ. (Japan), 2. Graduate School of Biomedical Eng., Tohoku Univ. (Japan))

9:45 AM - 10:00 AM

[G-5-03] Damascene Compatible Low Thermal Budget Fine-Pitch Copper Hybrid Boding with Ultra-Thin Surface Passivation

^○Hemanth Kuamr Cheemalamarri¹, Gim Guan Chen¹, Hongyu Li¹, Chandra Rao Bhesetti¹, Nagendra Sekhar Vasarla¹, Nandini Venkataraman¹, King Jien Chui¹, Srinivasa Rao Vempati¹, Navab Singh¹ (1. Institute of Microelectronics, Agency for Science, Technology and Research (A*STAR), Singapore (Singapore))

10:00 AM - 10:15 AM

[G-5-04] Middle-End of Line Si FinFETs Using Laser-Liquid-Phase-Epitaxy Technique for Monolithic 3DIC

^○Bo- Jheng Shih^1,2, Yu-Ming Pan¹, Hao-Tung Chung¹, Nei-Chih Lin², Chih-Chao Yang², Po-Tsang Huang¹, Huang-Chung Cheng¹, Chang-Hong Shen², Jia-Min Shieh², Wen-Fa Wu², Kuan-Neng Chen¹, Chenming Hu^1,3 (1. Univ. of Yang Ming Chiao Tung (Taiwan), 2. Inst. of Taiwan Semiconductor Research (Taiwan), 3. Univ. of California, Berkeley (United States of America))

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