[PS-1] 01: Advanced CMOS: Material Science / Process Engineering / Device Technology

2023年9月7日(木) 15:00 〜 17:00 Shirotori Hall (Nagoya Congress Center)

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[PS-1-01] Amorphous Si-rich Mo silicide films for advanced source/drain contacts

^○Naoya Okada¹, Noriyuki Uchida¹, Toshihiko Kanayama¹ (1. AIST (Japan))

[PS-1-02] A Simple Way to Fabricate Si N-/P-Channels CFET Using Si/Ge Multilayer Epitaxy, Direct S/D Implantation and Ge Selective Etching

^○Guang- Li Luo¹, Chun-Lin Chu¹, Szu-Hung Chen¹, Wei-Yuan Chang¹, Wen-Fa Wu¹ (1. Taiwan Semiconductor Research Institute (Taiwan))

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[PS-1-03] Effects of HfO₂ and ZrO₂ Seed Layers on the Transition from Antiferroelectric (AFE) to Ferroelectric (FE) of Rich Zr Composition HfO₂-based Film

^○Peilin Zeng¹, Yue Peng¹, Wenwu Xiao², Yan Liu¹, Genquan Han^1,3, Yue Hao¹ (1. Wide Bandgap Semiconductor Technology Disciplines State Key aboratory,School of Microelectronics.Xidian University (China), 2. Xi’an UnilC Semiconductors CompanyLtd. (China), 3. Hangzhou Institute of Technology.Xidian University, Hangzhou (China))

[PS-1-04] Generative Adversarial Network Applied to Neuroevolution-based Compact Device models

^○Bing- Ru Jiang¹, Han-Chun Tung¹, Ting Tsai¹, Ming-Hsien Hsu¹, Albert Lin¹, Pei-Wen Li¹ (1. Natioanl Yang Ming Chiao Tung University (Taiwan))

[PS-1-05] Effective Detection of Micro-Potential Analytes with Self-Sensitivity Programmable pH Sensor Platform Based on a Multi-Functional Charge-Trap-Flash-Type Ion-Sensitive-Field-Effect-Transistor

^○Yeong-Ung Kim¹, Won-Ju Cho¹ (1. Kwangwoon Univ. (Korea))

[PS-1-06] Investigation of SiGe/Si Super Lattice GAAFET and CMOS Inverter

^○Heng- Jia Chang¹, Yi-Ju Yao², Ching-Ru Yang¹, Ting-Yu Tseng¹, Tsai-Jung Lin², Guang-Li Luo³, Fu-Ju Hou³, Yung-Chun Wu¹ (1. Department of Engineering and System Science, National Tsing Hua University (Taiwan), 2. College of Semiconductor Research, National Tsing Hua University (Taiwan), 3. Taiwan Semiconductor Research Institute (Taiwan))

[PS-1-07] Robustness of ferroelectric domain walls in Hf_0.5Zr_0.5O₂ thin films investigated by ac-signal response of dielectric properties

^○Shinji Migita¹, Shutaro Asanuma¹, Yukinori Morita¹, Hiroyuki Ota¹ (1. AIST (Japan))

[PS-1-08] Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Multi-Bit Content-Addressable Memories

^○Hongrui Zhang¹, Jiajia Chen¹, Chengji Jin¹, Gaobo Lin¹, Yan Liu², Xiao Yu¹, Genquan Han² (1. Zhejiang Lab, Hangzhou 311121 (China), 2. Xidian University, Xi’an 710071 (China))

[PS-1-09] Mobility Modeling of Nanosheet FET’s using Poisson-Schroedinger, Cellular Automaton Coupled Approach

^○Koichi Fukuda¹ (1. AIST (Japan))

[PS-1-10] Comparative Study of Radiation Damage Effects on FinFET and GAAFET

^○Ching-Hung Chang¹, Kuei-Shu Chang-Liao¹, Dun-Bao Ruan² (1. National Tsing Hua University (Taiwan), 2. Fuzhou University (China))

[PS-1-11] A DNN-Based Compact Modeling Technique for GAA Si NS FETs and Its Application in CMOS Circuit Simulation

Rajat - Butola¹, ^○Sekhar Reddy Kola¹, Yiming Li¹ (1. National Yang Ming Chiao Tung Univ. (Taiwan))

[PS-1-12] Engineering Oxidation State in Interfacial Layer of Ge nMOSFET with Ozone and Hydrogen Plasma Treatments on Ge

^○Cheng-Hsueh Wu¹, Kuei-Shu Chang-Liao¹, Dun-Bao Ruan² (1. National Tsing Hua University (Taiwan), 2. Fuzhou University (China))

[PS-1-13] Vertical Gate-All-Around SiGeSn/GeSn/SiGeSn Nanowire nFETs

Yannik Junk¹, Omar Concepción Diaz¹, Marvin Frauenrath^2,3, Florian Bärwolf⁴, Andreas Mai⁴, Jean-Michel Hartmann^2,3, Detlev Grützmacher¹, Dan Buca¹, ^○Qing-Tai Zhao¹ (1. Peter-Grünberg-Institut (PGI-9) and JARA-FIT, Forschungszentrum Jülich (Germany), 2. CEA-LETI, MINATEC Campus, F-38054 Grenoble (France), 3. Univ. of Grenoble Alps (France), 4. IHP-Leibniz-Institut für innovative Mikroelektronik, 15236 Frankfurt (Oder) (Germany))

[PS-1-14] Nano CMOS Devices Layout Optimization for Super-350GHz f_MAX in mmWave and Sub-THz CMOS Applications

^○Adhi Cahyo Wijaya¹, Jinq Min Lin¹, Jyh Chyurn Guo¹ (1. National Yang Ming Chiao Tung University (Taiwan))

[PS-1-15] Enhancing Perceptual Artificial Intelligence Systems with a Dynamically Reconfigurable CMOS-Compatible Synaptic Transistor

^○Dong Hee LEE¹, Won-Ju Cho¹ (1. Kwangwoon university, Korea (Korea))

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