Sub-20nm gate length p-FinFETs device performance improvement using TEM/EDX and NBD based TCAD calibrations.

Pierre EYBEN

doi:https://doi.org/10.7567/SSDM.2023.F-1-02

講演情報

Oral Presentation

01: Advanced CMOS: Material Science / Process Engineering / Device Technology

[F-1] Modeling, Simulation and Characterization

2023年9月6日(水) 14:00 〜 15:45 Room F (224, Bldg. 2)

Session Chairs: Satofumi Souma (Kobe Univ.), Hidetoshi Oishi (Sony Semiconductor Solutions Corp.)

14:15 〜 14:30

[F-1-02] Sub-20nm gate length p-FinFETs device performance improvement using TEM/EDX and NBD based TCAD calibrations.

^○Pierre EYBEN¹, Pierre De Keersgieter¹, Philippe Matagne¹, Thomas Chiarella¹, Clément Porret¹, Andriy Hikavyy¹, Yong Kong Siew¹, Ludovic Goux¹, Jérôme Mitard¹, Naoto Horiguchi¹ (1. Imec (Belgium))

https://doi.org/10.7567/SSDM.2023.F-1-02

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講演情報

[F-1] Modeling, Simulation and Characterization

[F-1-02] Sub-20nm gate length p-FinFETs device performance improvement using TEM/EDX and NBD based TCAD calibrations.

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